ZHCSNE6 August   2021 TPS1653

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and In-Rush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Overload and Short Circuit Protection
        1. 8.3.3.1 Overload Protection
        2. 8.3.3.2 Short Circuit Protection
          1. 8.3.3.2.1 Start-Up With Short-Circuit On Output
      4. 8.3.4  Current Monitoring Output (IMON)
      5. 8.3.5  FAULT Response (FLT)
      6. 8.3.6  Power Good Output (PGOOD)
      7. 8.3.7  IN, P_IN, OUT and GND Pins
      8. 8.3.8  Thermal Shutdown
      9. 8.3.9  Low Current Shutdown Control (SHDN)
      10. 8.3.10 Enable Input (EN)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 9.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 48-V Power Amplifier Protection for Telecom Radios
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 58 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
UVLO INPUT (UVLO)
UVLO_ton(dly) UVLO switch turnon delay UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dVdT) ≥ 10 nF,  [C(dVdT) in nF] 742 + 49.5 x C(dVdT) µs
UVLO_toff(dly) UVLO switch turnoff delay UVLO↓(20 mV below V(UVLOF)) to FLT↓ 9 11 16 µs
tUVLO_FLTdly) UVLO to fault de-assertion delay UVLO↑  to FLT ↑ delay 500 617 700 µs
ENABLE INPUT (EN)
EN_tOFF(dly) Enable turn-off delay EN↑ (20 mV above V(OVPR)) to FLT↓ 8.5 11 14 µs
EN_ton(dly) Enable turn-on delay EN↓ (100 mV below V(OVPF)) to FET ON  C(dVdT) ≥ 10 nF,  [C(dVdT) in nF] 150 + 49.5 x C(dVdT) µs
SHUTDOWN CONTROL INPUT (SHDN)
tSD(dly) SHUTDOWN entry delay SHDN↓ (below V(SHUTF)) to FET OFF 0.8 1 1.5 µs
CURRENT LIMIT
tFASTTRIP(dly) Hot-short response time I(OUT) > I(SCP) 1 µs
tFASTTRIP(dly) Soft short response I(FASTTRIP) < I(OUT) < I(SCP) 2.2 3.2 4.5 µs
tCL_ILIM(dly) Maximum duration in current limit 129 162 202 ms
tCB(dly) Maximum duration in 2x Pulse current limiting  I(OL) < I(OUT) ≤ I(2xOL) 20 25.5 31 ms
tCL_ILIM_FLT(dly) FLT delay in current limit 1.09 1.3 1.6 ms
OUTPUT RAMP CONTROL (dVdT)
t(FASTCHARGE) Output ramp time in fast charging C(dVdT) = Open, 10% to 90% V(OUT), C(OUT) = 1 µF; V(IN) = 24V 350 495 700 µs
t(dVdT) Output ramp time C(dVdT) = 22 nF, 10% to 90% V(OUT), V(IN) = 24V 8.35 ms
POWER GOOD (PGOOD)
tPGOODR PGOOD delay (deglitch) time Rising edge 8 11.5 13 ms
tPGOODF PGOOD delay (deglitch) time Falling edge 8 10 13 ms
FAULT FLAG (FLT)
tCB_FLT(dly) FLT assertion delay in Pulse over current limiting Delay from I(OUT) > I(OL) to FLT↓. 22 25.5 30 ms
THERMAL PROTECTION
t(TSD_retry) Retry delay in TSD MODE = GND 500 648 800 ms
t(Treg_timeout) Thermal Regulation timeout 1 1.3 1.6 s