ZHCSLO8D November   2020  – January 2022 TMUX6208 , TMUX6209

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Source or Drain Continuous Current
    6. 7.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 7.7  ±15 V Dual Supply: Switching Characteristics 
    8. 7.8  36 V Single Supply: Electrical Characteristics 
    9. 7.9  36 V Single Supply: Switching Characteristics 
    10. 7.10 12 V Single Supply: Electrical Characteristics 
    11. 7.11 12 V Single Supply: Switching Characteristics 
    12. 7.12 ±5 V Dual Supply: Electrical Characteristics 
    13. 7.13 ±5 V Dual Supply: Switching Characteristics 
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Transition Time
    5. 8.5  tON(EN) and tOFF(EN)
    6. 8.6  Break-Before-Make
    7. 8.7  tON (VDD) Time
    8. 8.8  Propagation Delay
    9. 8.9  Charge Injection
    10. 8.10 Off Isolation
    11. 8.11 Crosstalk
    12. 8.12 Bandwidth
    13. 8.13 THD + Noise
    14. 8.14 Power Supply Rejection Ratio (PSRR)
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Rail-to-Rail Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 9.3.5 Fail-Safe Logic
      6. 9.3.6 Latch-Up Immune
      7. 9.3.7 Ultra-Low Charge Injection
    4. 9.4 Device Functional Modes
    5. 9.5 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Design Requirements
    4. 10.4 Detailed Design Procedure
    5. 10.5 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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9.3.7 Ultra-Low Charge Injection

Figure 9-1 shows that the TMUX620x have a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

GUID-3F5BCCB4-1805-40B4-999C-C464C07E28E9-low.gifFigure 9-1 Transmission Gate Topology

The TMUX620x contain specialized architecture to reduce charge injection on the Drain (D). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the Source (Sx) instead of the Drain (D). As a general rule of thumb, Cp should be 20x larger than the equivalent load capacitance on the Drain (D). Figure 9-2 shows charge injection variation with different compensation capacitors on the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a 100pF load capacitance.

Figure 9-2 Charge Injection Compesation