ZHCS864M April 2009 – January 2019 TMS320F28030 , TMS320F28031 , TMS320F28032 , TMS320F28033 , TMS320F28034 , TMS320F28035
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tw(RSL1) | Pulse duration, XRS driven by device | 600 | μs | |||
tw(WDRS) | Pulse duration, reset pulse generated by watchdog | 512tc(OSCCLK) | cycles | |||
td(EX) | Delay time, address/data valid after XRS high | 32tc(OSCCLK) | cycles | |||
tINTOSCST | Start-up time, internal zero-pin oscillator | 3 | μs | |||
tOSCST(1) | On-chip crystal-oscillator start-up time | 1 | 10 | ms |
Figure 5-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.