UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
RESET remains low (de-asserted) as long as VDD is above the positive threshold (VIT+). If VDD falls below the negative threshold (VIT–), then reset is asserted and RESET goes to logic high VOH.
When VDD rise above VIT+, the delay circuit holds RESET high for the specified reset delay period (tD). When the reset delay has elapsed the RESET pin goes back to low logic and output goes to low voltage (VOL).
The push-pull variant does not require a pull-up resistor.