ZHCSJX8D August   2018  – February 2020 TLV803E , TLV809E , TLV810E

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      典型应用
  4. 修订历史记录
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagram
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
      2. 8.3.2 VDD Hysteresis
      3. 8.3.3 VDD Glitch Immunity
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active Low
        2. 8.3.4.2 RESET Output, Active High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

over operating range (TA = -40°C to 125°C), 1.7 V < VDD < 6 V, RUP = 10 kΩ to 6 V, 10 pF load at RESET pin, unless otherwise noted. Typical values are at 25°C, VDD = 3.3V and VIT- = 2.93 V. 

 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage 1.7 6 V
VIT- Input threshold voltage accuracy TA= -40 °C to125 °C -2 0.5 2 %
VHYS Hysteresis voltage Hysteresis from VIT- 0.9 1.2 1.5 %
IDD Supply current into VDD pin VDD=3.3 V; VDD>VIT+ (1) 0.25 1 µA
VDD=6 V 0.4 1.2 µA
TLV809E (Push-Pull Active-Low)
VPOR Power on reset voltage (2) VOL<= 300mV, IOUT (Sink) = 15 µA 700 mV
VOL Low level output voltage
 
VDD =1.7V, VDD < VIT-, IOUT (Sink) = 500 µA 300 mV
VDD= 3.3V, VDD < VIT-, IOUT (Sink) = 2 mA 300 mV
VOH High level output voltage
 

VDD = 6V, VDD > VIT+, IOUT (source) = 4 mA
0.8VDD V
VDD= 3.3V, VDD > VIT+, IOUT (source) = 2 mA 0.8VDD V
TLV803E (Open-Drain Active-Low)
VPOR Power on reset voltage (2) VOL <= 300 mV, IOUT (Sink) = 15 uA 700 mV
VOL Low level output voltage
 
VDD = 1.7 V, VDD < VIT-, IOUT = 500 µA 300 mV
VDD = 3.3 V, VDD < VIT-, IOUT = 2 mA 300 mV
Ilkg(OD) Open drain output leakage current VDD = VPULLUP = 6 V, VDD > VIT+ 100 350 nA
TLV810E (Push-Pull Active-High) (3)
VOH High level output voltage 
 
VDD= 3.3V, VDD < VIT-, IOUT (source) = 2 mA 0.8VDD V
VDD = 1.7V, VDD < VIT-, IOUT (source) = 500 uA 0.8VDD V
VPOR Power on Reset Voltage VOH >= 720 mV, IOUT (Source) = 15 uA 900 mV
VOL Low level output voltage
 
VDD = 6V, VDD > VIT+,  IOUT (Sink) = 2 mA 300 mV
VDD= 3.3V, VDD > VIT+, IOUT (Sink) = 500 µA 300 mV
VIT+ = VIT- + VHYS
Minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined.
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