The TLV803 family of supervisory circuits provides circuit initialization and timing supervision. The TLV853 and TLV863 are both functionally equivalent to the TLV803. These devices output a logic low whenever VDD drops below the negative-going threshold voltage (VIT–). The output, RESET, remains low for approximately 200 ms after the VDD voltage exceeds the positive-going threshold voltage (VIT– + Vhys). These devices are designed to ignore fast transients on the VDD pin.
The TLV803 has built-in rejection of fast transients on the VDD pin. The rejection of transients depends on both the duration and the amplitude of the transient. The amplitude of the transient is measured from the bottom of the transient to the negative threshold voltage of the TLV803, as shown in Figure 8.
The TLV803 does not respond to transients that are fast duration/low amplitude or long duration/small amplitude. Figure 5 shows the relationship between the transient amplitude and duration needed to trigger a reset. Any combination of duration and amplitude above the curve generates a reset signal.
The TLV803 output is valid when VDD is greater than 1.1 V. When VDD is less than 1.1 V, the output transistor turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to the pull-up resistor. Figure 9 shows a typical waveform for power-up, assuming the RESET pin has a pull-up resistor connected to the VDD pin.
Some microcontrollers have bidirectional reset pins that act as both inputs and outputs. In a situation where the TLV803 is pulling the RESET line low while the microcontroller is trying the force the RESET line high, a series resistor should be placed between the output of the TLV803 and the RESET pin of the microcontroller to protect against excessive current flow. Figure 10 shows the connection of the TLV803 to a microcontroller using a series resistor to drive a bidirectional RESET line.
When the voltage on VDD is greater than 1.1 V, the RESET signal asserts when VDD is less than VIT– and deasserts when VDD is greater thanVIT–.
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (power-up reset voltage), both outputs are in a high-impedance state.