SBVS148D October   2010  – January 2015 TLV704

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Regulator Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Junction Temperature
    4. 10.4 Estimating Junction Temperature
    5. 10.5 Package Mounting
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DBV|5
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

Input and output capacitors should be placed as close to the device pins as possible. To avoid interference of noise and ripple on the board, TI recommends designing the board with separate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the ground connection for the output capacitor should be connected directly to the device GND pin.

10.2 Layout Example

TLV704_layout_dbv_bvs148.gifFigure 18. Layout Example for the DBV Package

10.3 Power Dissipation and Junction Temperature

To ensure reliable operation, worst-case junction temperature should not exceed 125°C. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max).

The maximum power dissipation limit is determined using Equation 1:

Equation 1. Q_pdmax_rtja_sbvs148.gif

where:

TJmax is the maximum allowable junction temperature.

RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Information table).

TA is the ambient temperature.

The regulator dissipation is calculated using Equation 2:

Equation 2. Q_pd_vi_vo-BVS047.gif

Power dissipation resulting from quiescent current is negligible.

10.4 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the Thermal Informationtable and are used in accordance with Equation 3.

Equation 3. q_wjt-wjb_bvs204.gif

where

  • PD is the power dissipated as explained in Thermal Information
  • TT is the temperature at the center-top of the device package
  • TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge.

10.5 Package Mounting

Solder pad footprint recommendations for the TLV704 are available from the TI's website at www.ti.com through the TLV704 series product folders. The recommended land pattern for the DBV package is appended to this data sheet.