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  • TL08xx FET 输入运算放大器

    • ZHCSMO4N February   1977  – June 2024 TL081 , TL081A , TL081B , TL081H , TL082 , TL082A , TL082B , TL082H , TL084 , TL084A , TL084B , TL084H

      PRODUCTION DATA  

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  • TL08xx FET 输入运算放大器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information for Single Channel
    5. 5.5  Thermal Information for Dual Channel
    6. 5.6  Thermal Information for Quad Channel
    7. 5.7  Electrical Characteristics: TL08xH
    8. 5.8  Electrical Characteristics (DC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM
    9. 5.9  Electrical Characteristics (AC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM
    10. 5.10 Typical Characteristics: TL08xH
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Total Harmonic Distortion
      2. 7.3.2 Slew Rate
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Inverting Amplifier Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 General Applications
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明

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  • DYY|14
  • PW|14
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Data Sheet

TL08xx FET 输入运算放大器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

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1 特性

  • 高压摆率：20V/μs（TL08xH，典型值）
  • 低失调电压：1mV（TL08xH，典型值）
  • 低失调电压漂移：2μV/°C
  • 低功耗：940μA/通道（TL08xH，典型值）
  • 宽共模和差分
    电压范围
    • 共模输入电压范围
      包括 VCC+
  • 低输入偏置和失调电流
  • 低噪声：
    f = 1kHz 时，Vn = 18nV/√Hz（典型值）
  • 输出短路保护
  • 低总计谐波失真：0.003%（典型值）
  • 宽电源电压：
    ±2.25V 至 ±20V，4.5V 至 40V

2 应用

  • 太阳能：串式和中央逆变器
  • 电机驱动器：交流和伺服驱动控制及功率级模块
  • 单相在线式 UPS
  • 三相 UPS
  • 专业音频混合器
  • 电池测试设备

3 说明

TL08xH（TL081H、TL082H 和 TL084H）系列器件是业界通用的 TL08x（TL081、TL082 和 TL084）器件的下一代版本。这些器件为成本敏感型应用提供了卓越的价值，其特性包括低失调电压（1mV，典型值）、高压摆率 (20V/μs) 和正电源的共模输入。得益于高 ESD（1.5kV，HBM）、集成 EMI 和射频滤波器以及 –40°C 至 125°C 的完整运行温度范围，TL08xH 器件可用于要求严苛的应用。

器件信息
器件型号 封装(1) 本体尺寸（标称值）(2)
TL081x P（PDIP，8） 9.59mm × 6.35mm
DCK（SC70，5） 2mm × 1.25mm
PS（SO，8） 6.2mm × 5.3mm
D（SOIC，8） 4.9mm × 3.9mm
DBV（SOT-23，5） 2.9mm × 1.6mm
TL082x P（PDIP，8） 9.59mm × 6.35mm
PS（SO，8） 6.2mm × 5.3mm
D（SOIC，8） 4.9mm × 3.9mm
DDF（SOT-23，8） 2.9mm × 1.6mm
PW（TSSOP，8） 4.4mm × 3mm
TL082M JG（CDIP，8） 9.6mm × 6.67mm
FK（LCCC，20） 8.89mm × 8.89mm
TL084x N（PDIP，14） 19.3mm × 6.35mm
NS（SO，14） 10.3mm × 5.3mm
D（SOIC，14） 8.65mm × 3.91mm
DYY（SOT-23，14） 4.2mm × 2mm
PW（TSSOP，14） 5mm × 4.4mm
TL084M J（CDIP，14） 19.56mm × 6.67mm
FK（LCCC，20） 8.89mm × 8.89mm
(1) 有关更多信息，请参阅节 11。
(2) 本体尺寸（长 x 宽）为标称值，不包括引脚。
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H 逻辑符号逻辑符号

4 Pin Configuration and Functions

TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL081H DBV Package,5-Pin SOT-23 (Top View)Figure 4-1 TL081H DBV Package,
5-Pin SOT-23
(Top View)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL081H D Package,8-Pin SOIC(Top View)
NC- no internal connection
Figure 4-3 TL081H D Package,
8-Pin SOIC
(Top View)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL081H DCK Package,5-Pin SC70(Top View)Figure 4-2 TL081H DCK Package,
5-Pin SC70
(Top View)
Table 4-1 Pin Functions: TL081H
PIN TYPE(1) DESCRIPTION
NAME DBV DCK D
IN– 4 3 2 I Inverting input
IN+ 3 1 3 I Noninverting input
NC — — 8 — Do not connect
NC — — 1 — Do not connect
NC — — 5 — Do not connect
OUT 1 4 6 O Output
VCC– 2 2 4 — Power supply
VCC+ 5 5 7 — Power supply
(1) I = input, O = output
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL081x D, P, and PS Package,8-Pin SOIC, PDIP, and SO(Top View)
NC- no internal connection
Figure 4-4 TL081x D, P, and PS Package,
8-Pin SOIC, PDIP, and SO
(Top View)
Table 4-2 Pin Functions: TL081x
PIN TYPE(1) DESCRIPTION
NAME NO.
IN– 2 I Inverting input
IN+ 3 I Noninverting input
NC 8 — Do not connect
OFFSET N1 1 — Input offset adjustment
OFFSET N2 5 — Input offset adjustment
OUT 6 O Output
VCC– 4 — Power supply
VCC+ 7 — Power supply
(1) I = input, O = output
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL082x D, DDF, DGK, JG, P, PS, and PW Package,8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP(Top View) Figure 4-5 TL082x D, DDF, DGK, JG, P, PS, and PW Package,
8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP
(Top View)
Table 4-3 Pin Functions: TL082x
PIN TYPE(1) DESCRIPTION
NAME NO.
1IN– 2 I Inverting input
1IN+ 3 I Noninverting input
1OUT 1 O Output
2IN– 6 I Inverting input
2IN+ 5 I Noninverting input
2OUT 7 O Output
VCC– 4 — Power supply
VCC+ 8 — Power supply
(1) I = input, O = output
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL082 FK Package,20-Pin LCCC(Top View)
NC- no internal connection
Figure 4-6 TL082 FK Package,
20-Pin LCCC
(Top View)
Table 4-4 Pin Functions: TL082x
PIN TYPE(1) DESCRIPTION
NAME NO.
1IN– 5 I Inverting input
1IN+ 7 I Noninverting input
1OUT 2 O Output
2IN– 15 I Inverting input
2IN+ 12 I Noninverting input
2OUT 17 O Output
NC 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 — Do not connect
VCC– 10 — Power supply
VCC+ 20 — Power supply
(1) I = input, O = output
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL084x D, N, NS, PW, J, and DYY Package,14-Pin SOIC, PDIP, SO, TSSOP, CDIP, and SOT-23 (14)(Top View) Figure 4-7 TL084x D, N, NS, PW, J, and DYY Package,
14-Pin SOIC, PDIP, SO, TSSOP, CDIP, and SOT-23 (14)
(Top View)
Table 4-5 Pin Functions: TL084x
PIN TYPE(1) DESCRIPTION
NAME NO.
1IN– 2 I Inverting input
1IN+ 3 I Noninverting input
1OUT 1 O Output
2IN– 6 I Inverting input
2IN+ 5 I Noninverting input
2OUT 7 O Output
3IN– 9 I Inverting input
3IN+ 10 I Noninverting input
3OUT 8 O Output
4IN– 13 I Inverting input
4IN+ 12 I Noninverting input
4OUT 14 O Output
VCC– 11 — Power supply
VCC+ 4 — Power supply
(1) I = input, O = output
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H TL084 FK Package,20-Pin LCCC(Top View)
NC- no internal connection
Figure 4-8 TL084 FK Package,
20-Pin LCCC
(Top View)
Table 4-6 Pin Functions: TL084x
PIN TYPE(1) DESCRIPTION
NAME NO.
1IN– 3 I Inverting input
1IN+ 4 I Noninverting input
1OUT 2 O Output
2IN– 9 I Inverting input
2IN+ 8 I Noninverting input
2OUT 10 O Output
3IN– 13 I Inverting input
3IN+ 14 I Noninverting input
3OUT 12 O Output
4IN– 19 I Inverting input
4IN+ 18 I Noninverting input
4OUT 20 O Output
NC 1, 5, 7, 11, 15, 17 — Do not connect
VCC– 16 — Power supply
VCC+ 6 — Power supply
(1) I = input, O = output

5 Specifications

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–)  All NS and PS packages; All TL08xM devices –0.3 36 V
All other devices 0 42 V
Signal input pins Common-mode voltage (3) All NS and PS packages; All TL08xM devices (V–) – 0.3 (V–) + 36 V
All other devices (V–) – 0.5 (V+) + 0.5 V
Differential voltage (3) All NS and PS packages; All TL08xM devices (4) (V–) – 0.3 (V–) + 36 V
All other devices VS + 0.2 V
Current (3) All NS and PS packages; All TL07xM devices 50 mA
All other devices –10 10 mA
Output short-circuit (2) Continuous
Operating ambient temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Case temperature for 60 seconds - FK package 260 °C
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5V beyond the supply rails must be current limited to 10 mA or less.
(4) Differential voltage only limited by input voltage.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage, (V+) – (V–) All NS and PS packages; All TL08xM devices(1) 10 30 V
All other devices 4.5 40 V
VI Input voltage range All NS and PS packages; All TL08xM devices (V–) + 2 (V+) + 0.1 V
All other devices (V–) + 4 (V+) + 0.1 V
TA Specified temperature TL08xM –55 125 °C
TL08xH –40 125 °C
TL08xI –40 85 °C
TL08xC 0 70 °C
(1) V+ and V– are not required to be of equal magnitude, provided that the total VS (V+ – V–) is between 10V and 30V.

5.4 Thermal Information for Single Channel

THERMAL METRIC (1) TL081xx UNIT
D 
(SOIC)		 DCK
(SC70)		 DBV 
(SOT-23)		 P
(PDIP)		 PS 
(SO)
8 PINS 5 PINS 5 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 158.8 217.5 212.2 85 95 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 98.6 113.1 111.1 – – °C/W
RθJB Junction-to-board thermal resistance 102.3 63.8 79.4 – – °C/W
ψJT Junction-to-top characterization parameter 45.8 34.8 51.8 – – °C/W
ψJB Junction-to-board characterization parameter 101.5 63.5 79.0 – – °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.5 Thermal Information for Dual Channel

THERMAL METRIC (1) TL082xx UNIT
D 
(SOIC)		 DDF
(SOT-23)		 FK
(LCCC)		 JG
(CDIP)		 P 
(PDIP)		 PS
(SO)		 PW
(TSSOP)		 U
(CFP)
8 PINS 8 PINS 20 PINS 8 PINS 8 PINS 8 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 147.8 181.5 – – 85 95 200.3 169.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 88.2 112.5 5.61 15.05 – – 89.4 62.1 °C/W
RθJB Junction-to-board thermal resistance 91.4 98.2 – – – – 131.0 176.2 °C/W
ψJT Junction-to-top characterization parameter 36.8 17.2 – – – – 22.2 48.4 °C/W
ψJB Junction-to-board characterization parameter 90.6 97.6 – – – – 129.3 144.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A – – – – N/A 5.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.6 Thermal Information for Quad Channel

THERMAL METRIC (1) TL084xx UNIT
D
(SOIC)		 DYY
(SOT-23)		 FK
(TSSOP)		 J
(TSSOP)		 N
(TSSOP)		 NS
(TSSOP)		 PW
(TSSOP)		 W
(TSSOP)
14 PINS 14 PINS 20 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 114.2 153.2 – – 80 76 – 128.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 70.3 88.7 5.61 14.5 – – 14.5 56.1 °C/W
RθJB Junction-to-board thermal resistance 70.2 65.4 – – – – – 127.6 °C/W
ψJT Junction-to-top characterization parameter 28.8 9.5 – – – – – 29 °C/W
ψJB Junction-to-board characterization parameter 69.8 65.0 – – – – – 106.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A – – – – – 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.7 Electrical Characteristics: TL08xH

For VS = (VCC+) – (VCC–) = 4.5V to 40V (±2.25V to ±20V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±1 ±4 mV
TA = –40°C to 125°C ±5
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±2 µV/℃
PSRR Input offset voltage versus power supply VS = 5V to 40V, VCM = VS / 2 TA = –40°C to 125°C ±1 ±10 μV/V
Channel separation f = 0Hz 10 µV/V
INPUT BIAS CURRENT
IB Input bias current  ±1 ±120 pA
DCK and DBV packages ±1 ±300 pA
TA = –40°C to 125°C (1) ±5 nA
IOS Input offset current  ±0.5 ±120 pA
DCK and DBV packages ±0.5 ±250 pA
TA = –40°C to 125°C (1) ±5 nA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz   9.2 μVPP
  1.4   µVRMS
eN Input voltage noise density f = 1kHz 37   nV/√Hz
f = 10kHz   21  
iN Input current noise f = 1kHz   80 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (VCC–) + 1.5 (VCC+) V
CMRR Common-mode rejection ratio VS = 40V, (VCC–) + 2.5V < VCM < (VCC+) – 1.5V 100 105 dB
TA = –40°C to 125°C 95 dB
VS = 40V, (VCC–) + 2.5V < VCM < (VCC+) 90 105 dB
TA = –40°C to 125°C 80 dB
INPUT CAPACITANCE
ZID Differential 100 || 2 MΩ ||pF
ZICM Common-mode 6 || 1 TΩ ||pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40V, VCM = VS / 2,
(VCC–) + 0.3V < VO < (VCC+) –  0.3V		 TA = –40°C to 125°C 118 125 dB
AOL Open-loop voltage gain VS = 40V, VCM = VS / 2, RL = 2kΩ, (VCC–) + 1.2V < VO < (VCC+) –  1.2V TA = –40°C to 125°C 115 120 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 5.25 MHz
SR Slew rate VS = 40V, G = +1, CL = 20pF 20 V/μs
tS Settling time To 0.1%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 0.63 μs
To 0.1%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 0.56
To 0.01%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 0.91
To 0.01%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 0.48
Phase margin G = +1, RL = 10kΩ, CL = 20pF 56 °
Overload recovery time VIN  × gain > VS 300 ns
THD+N Total harmonic distortion + noise VS = 40V, VO = 6VRMS, G = +1, f = 1kHz 0.00012 %
EMIRR EMI rejection ratio f = 1GHz 53 dB
OUTPUT
  Voltage output swing from rail Positive rail headroom VS = 40V, RL = 10kΩ   115 210 mV
VS = 40V, RL = 2kΩ   520 965
Negative rail headroom VS = 40V, RL = 10kΩ   105 215
VS = 40V, RL = 2kΩ   500 1030
ISC Short-circuit current ±26 mA
CLOAD Capacitive load drive 300
 pF
ZO Open-loop output impedance f = 1MHz, IO = 0 A 125 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 937.5 1125 µA
IO = 0 A, (TL081H) 960 1156
IO = 0 A TA = –40°C to 125°C 1130
IO = 0 A, (TL082H) 1143
IO = 0 A, (TL071H) 1160
Turn-On Time At TA = 25°C, VS = 40V, VS ramp rate > 0.3V/µs
 60 μs
(1) Max IB and Ios data is specified based on characterization results.

5.8 Electrical Characteristics (DC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM

For VS = (VCC+) – (VCC–) = ±15V at TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS(1)(2) MIN TYP MAX UNIT
 
VOS Input offset voltage
 VO = 0V
RS = 50 Ω		 TL08xC 3 10 mV
TA = Full range 13
TL08xAC 3 6
TA = Full range 7.5
TL08xBC 2 3
TA = Full range 5
TL08xI 3 6
TA = Full range 8
TL081M, TL082M 3 6
TA = Full range 9
TL084M 3 9
TA = Full range 15
dVOS/dT Input offset voltage drift VO = 0V, RS = 50 Ω TA = Full range ±18 µV/℃
IOS Input offset current  VO = 0V TL08xC 5 100 pA
TA = Full range 10 nA
TL08xAC, TL08xBC, TL08xI 5 100 pA
TA = Full range 2 nA
TL08xM 5 100 pA
TA = Full range 20 nA
IB Input bias current  VO = 0V TL08xC, TL08xAC,
TL08xBC, TL08xI		 65 200 pA
TA = Full range 7 nA
TL081M, TL082M 65 200 pA
TA = Full range 50 nA
TL084M 65 200 pA
TA = Full range 20 nA
VCM Common-mode voltage range ±11 –12 to 15 V
VOM Maximum peak output voltage swing RL = 10kΩ ±12 ±13.5 V
RL ≥ 10kΩ TA = Full range ±12
RL ≥ 2kΩ ±10
AOL Open-loop voltage gain VO = 0V TL08xC 25 200 V/mV
TA = Full range 15
TL08xAC, TL08xBC, TL08xI 50 200
TA = Full range 25
TL08xM 35 200
TA = Full range 15
GBW Gain-bandwidth product All NS and PS packages; All TL08xM devices 3 MHz
All other devices  5.25
RID Common-mode input resistance 1 TΩ
CMRR Common-mode rejection ratio VIC = VICR(min)
VO = 0V
RS = 50 Ω		 TL08xC 70 100 dB
TL08xAC, TL08xBC, TL08xI 75 100
TL08xM 80 86
PSRR Input offset voltage versus power supply VS = ±9V to ± 18V
VO = 0V
RS = 50 Ω		 TL08xC 70 100 dB
TL08xAC, TL08xBC, TL08xI 80 100
TL08xM 80 86
IQ Quiescent current per amplifier VO = 0V; no load 1.4 2.5 mA
Channel separation f = 0Hz 1 µV/V
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C for the TL07xC, TL07xAC, and TL07xBC; TA = –40°C to 85°C for the TL07xI; and TA = –55°C to 125°C for the TL07xM.

5.9 Electrical Characteristics (AC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM

For VS = (VCC+) – (VCC–) = ±15V at TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
 
SR Slew rate  VI = 10V, CL = 100pF, RL = 2kΩ TL08xM 5 20 V/μs
TL08xC, TL08xAC,
TL08xBC, TL08xI		 8 20 V/μs
tS Settling time VI = 20V, CL = 100pF, RL = 2kΩ 0.1 μs
20%
eN Input voltage noise density All PS and NS packages; All TL08xM devices RS = 20 Ω, f = 1kHz 18   nV/√Hz
All other devices  f = 1kHz 37   nV/√Hz
f = 10kHz   21  
EN Input voltage noise All PS and NS packages; All TL08xM devices RS = 20 Ω, f = 10Hz to 10kHz   4 μVRMS
All other devices f = 0.1Hz to 10Hz   1.4   µVRMS
iN Input current noise RS = 20 Ω, f = 1kHz   10 fA/√Hz
Phase margin TL08xC, TL08xAC, TL08xBC, TL08xI G = +1, RL = 10kΩ, CL = 20pF 56 °
Overload recovery time VIN  × gain > VS 300 ns
THD+N Total harmonic distortion + noise All PS and NS packages; All TL08xM devices VO = 6VRMS, RL ≥ 2kΩ, f = 1kHz, G = +1, RS ≤ 1kΩ 0.003 %
All other devices  VS = 40V, VO = 6VRMS, G = +1, f = 1kHz 0.00012 %
EMIRR EMI rejection ratio TL08xC, TL08xAC, TL08xBC, TL08xI f = 1GHz 53 dB
ZO Open-loop output impedance TL07xC, TL07xAC, TL07xBC, TL07xI f = 1MHz, IO = 0 A 125 Ω

5.10 Typical Characteristics: TL08xH

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted)

TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage Production Distribution
TA = 25°C
Figure 5-1 Offset Voltage Production Distribution
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage vs Temperature
VCM = VS / 2
Figure 5-3 Offset Voltage vs Temperature
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage vs Common-Mode Voltage
TA = 125°C
Figure 5-5 Offset Voltage vs Common-Mode Voltage
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage vs Power Supply
 
Figure 5-7 Offset Voltage vs Power Supply
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Closed-Loop Gain vs FrequencyFigure 5-9 Closed-Loop Gain vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Input Bias Current vs TemperatureFigure 5-11 Input Bias Current vs Temperature
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Output Voltage Swing vs Output Current (Sinking)
 
Figure 5-13 Output Voltage Swing vs Output Current (Sinking)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H CMRR vs Temperature (dB)
f = 0Hz
Figure 5-15 CMRR vs Temperature (dB)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H 0.1-Hz to 10-Hz NoiseFigure 5-17 0.1-Hz to 10-Hz Noise
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H THD+N Ratio vs Frequency
BW = 80kHz, VOUT = 1VRMS
Figure 5-19 THD+N Ratio vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Quiescent Current vs Supply Voltage
VCM = VS / 2
Figure 5-21 Quiescent Current vs Supply Voltage
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Open-Loop Voltage Gain vs Temperature (dB)Figure 5-23 Open-Loop Voltage Gain vs Temperature (dB)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Small-Signal Overshoot vs Capacitive Load
G = –1, 25-mV output step
Figure 5-25 Small-Signal Overshoot vs Capacitive Load
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Phase Margin vs Capacitive Load
 
Figure 5-27 Phase Margin vs Capacitive Load
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Positive Overload Recovery
G = –10
Figure 5-29 Positive Overload Recovery
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Small-Signal Step Response, Rising
CL = 20pF, G = 1, 10-mV step response
Figure 5-31 Small-Signal Step Response, Rising
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Large-Signal Step Response (Rising)
CL = 20pF, G = 1
Figure 5-33 Large-Signal Step Response (Rising)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Large-Signal Step Response
CL = 20pF, G = 1
Figure 5-35 Large-Signal Step Response
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Maximum Output Voltage vs FrequencyFigure 5-37 Maximum Output Voltage vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H EMIRR (Electromagnetic Interference Rejection Ratio) vs FrequencyFigure 5-39 EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage Drift Distribution
 
Figure 5-2 Offset Voltage Drift Distribution
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage vs Common-Mode Voltage
TA = 25°C
Figure 5-4 Offset Voltage vs Common-Mode Voltage
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Offset Voltage vs Common-Mode Voltage
TA = –40°C
Figure 5-6 Offset Voltage vs Common-Mode Voltage
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Open-Loop Gain and Phase vs Frequency
 
Figure 5-8 Open-Loop Gain and Phase vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Input Bias Current vs Common-Mode VoltageFigure 5-10 Input Bias Current vs Common-Mode Voltage
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Output Voltage Swing vs Output Current (Sourcing)Figure 5-12 Output Voltage Swing vs Output Current (Sourcing)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H CMRR and PSRR vs Frequency
 
Figure 5-14 CMRR and PSRR vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H PSRR vs Temperature (dB)
f = 0Hz
Figure 5-16 PSRR vs Temperature (dB)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Input Voltage Noise Spectral Density vs FrequencyFigure 5-18 Input Voltage Noise Spectral Density vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H THD+N vs Output Amplitude
BW = 80kHz, f = 1kHz
Figure 5-20 THD+N vs Output Amplitude
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Quiescent Current vs Temperature
 
Figure 5-22 Quiescent Current vs Temperature
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Open-Loop Output Impedance vs FrequencyFigure 5-24 Open-Loop Output Impedance vs Frequency
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Small-Signal Overshoot vs Capacitive Load
G = 1, 10-mV output step
Figure 5-26 Small-Signal Overshoot vs Capacitive Load
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H No Phase Reversal
VS = ±10V, VIN = VOUT
Figure 5-28 No Phase Reversal
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Negative Overload Recovery
G = –10
Figure 5-30 Negative Overload Recovery
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Small-Signal Step Response, Falling
CL = 20pF, G = 1, 10-mV step response
Figure 5-32 Small-Signal Step Response, Falling
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Large-Signal Step Response (Falling)
CL = 20pF, G = 1
Figure 5-34 Large-Signal Step Response (Falling)
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Short-Circuit Current vs Temperature
   
Figure 5-36 Short-Circuit Current vs Temperature
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Channel Separation vs FrequencyFigure 5-38 Channel Separation vs Frequency

6 Parameter Measurement Information

TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Test Figure 1Figure 6-1 Test Figure 1
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Test Figure 3Figure 6-3 Test Figure 3
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Test Figure 2Figure 6-2 Test Figure 2
TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H Test Figure 4Figure 6-4 Test Figure 4

 
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