ZHCSFB6D April 2016 – June 2021 THS4551
PRODUCTION DATA
The capacitive load of an ADC or some other next-stage device is commonly required to be driven. Directly connecting a capacitive load to the output pins of a closed-loop amplifier such as the THS4551 can lead to an unstable response; see the step response plots into a capacitive load (Figure 7-8, Figure 7-10, Figure 7-26, and Figure 7-28). One typical remedy to this instability is to add two small series resistors (RO) at the outputs of the THS4551 before the capacitive load. Figure 7-6 and Figure 7-24 illustrate parametric plots of recommended RO values versus differential capacitor load values and gains. Operating at higher noise gains requires lower RO values to obtain a ±0.5-dB flat response for the same capacitive load. Some direct parasitic loading is acceptable without a series RO that increases with gain setting (see Figure 7-8, Figure 7-10, Figure 7-26, and Figure 7-28 where the RO value is 0 Ω). Even when these plots suggest that a series RO is not required, good practice is to leave a place for the RO elements in a board layout (a 0-Ω value initially) for later adjustment in case the response appears unacceptable.
The rail-to-rail output stage of the THS4551 has an inductive characteristic in the open-loop output impedance at higher frequencies; see Figure 9-3. This inductive open-loop output impedance introduces added phase shift at the output pins for direct capacitive loads and feedback capacitors. Larger values of feedback capacitors (greater than 100 pF) can risk a low phase margin. Including a 10-Ω to 15-Ω series resistor with a feedback capacitor can be used to reduce this effect.
The TINA-TI™ simulation model does a good job of predicting these issues and illustrating the effect for different choices of capacitive load isolating resistors (RO) and different feedback capacitor configurations.