ZHCSPG0 December   2021 TCAN1167-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recomended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VSUP Pin
      2. 9.3.2  VCCOUT Pin
      3. 9.3.3  Digital Inputs and Outputs
        1. 9.3.3.1 TXD Pin
        2. 9.3.3.2 RXD Pin
      4. 9.3.4  GND
      5. 9.3.5  INH Pin
      6. 9.3.6  WAKE Pin
      7. 9.3.7  nRST Pin
      8. 9.3.8  SDO
      9. 9.3.9  nCS Pin
      10. 9.3.10 SCLK
      11. 9.3.11 SDI
      12. 9.3.12 CAN Bus Pins
      13. 9.3.13 Local Faults
        1. 9.3.13.1 TXD Dominant Timeout (TXD DTO)
        2. 9.3.13.2 Thermal Shutdown (TSD)
        3. 9.3.13.3 Under/Over Voltage Lockout
        4. 9.3.13.4 Unpowered Devices
        5. 9.3.13.5 Floating Terminals
        6. 9.3.13.6 CAN Bus Short Circuit Current Limiting
        7. 9.3.13.7 Sleep Wake Error Timer
      14. 9.3.14 Watchdog
        1. 9.3.14.1 Watchdog Error Counter
        2. 9.3.14.2 Watchdog SPI Control Programming
        3. 9.3.14.3 Watchdog Timing
        4. 9.3.14.4 Question and Answer Watchdog
          1. 9.3.14.4.1 WD Question and Answer Basic information
          2. 9.3.14.4.2 Question and Answer Register and Settings
          3. 9.3.14.4.3 WD Question and Answer Value Generation
        5. 9.3.14.5 Question and Answer WD Example
          1. 9.3.14.5.1 Example configuration for desired behavior
          2. 9.3.14.5.2 Example of performing a question and answer sequence
      15. 9.3.15 Bus Fault Detection and Communication
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Mode Description
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Silent Mode
        3. 9.4.1.3 Standby Mode
        4. 9.4.1.4 Sleep Mode
          1. 9.4.1.4.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 9.4.1.4.2 Local Wake-Up (LWU) via WAKE Input Terminal
        5. 9.4.1.5 Reset Mode
        6. 9.4.1.6 Fail-safe Mode
      2. 9.4.2 CAN Transceiver
        1. 9.4.2.1 CAN Transceiver Operation
        2. 9.4.2.2 CAN Transceiver Modes
          1. 9.4.2.2.1 CAN Off Mode
          2. 9.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 9.4.2.2.3 CAN Active
        3. 9.4.2.3 Driver and Receiver Function Tables
        4. 9.4.2.4 CAN Bus States
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Communication
      2. 9.5.2 Serial Clock Input (SCLK)
      3. 9.5.3 Serial Data Input (SDI)
      4. 9.5.4 Serial Data Output (SDO)
      5. 9.5.5 Chip Select Not (nCS)
      6. 9.5.6 Registers
        1. 9.5.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
        2. 9.5.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
        3. 9.5.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
        4. 9.5.6.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
        5. 9.5.6.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
        6. 9.5.6.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
        7. 9.5.6.7  WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
        8. 9.5.6.8  WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
        9. 9.5.6.9  WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
        10. 9.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
        11. 9.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
        12. 9.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
        13. 9.5.6.13 STATUS (address = 40h) [reset = 00h]
        14. 9.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
        15. 9.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
        16. 9.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
        17. 9.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
        18. 9.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
        19. 9.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
        20. 9.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
        21. 9.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
        22. 9.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
        23. 9.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
    3. 10.3 Application Curves
  11. 11Power Supply Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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9.5.1 Serial Peripheral Interface (SPI) Communication

The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out) and SCLK (Serial Clock). Each SPI transaction is a 16, 24 or 32 bits containing an address and read/write command byte followed by one to three data bytes. The data shifted out on the SDO pin for the transaction always starts with the Global Status Register (byte). This register provides the high level status information about the device status. The two data bytes which are the ‘response’ to the command byte are shifted out next. Data bytes shifted out during a write command is content of the registers prior to the new data being written and updating the registers. Data bytes shifted out during a read command are the content of the registers and the registers is not updated.

The SPI data input data on SDI is sampled on the low to high edge of the clock (SCLK). The SPI output data on SDO is changed on the high to low edge of the clock (SCLK).

When the device is in sleep mode, SPI communication is disabled, and the device must be woken up in order to resume SPI communciation.