10.1 Layout Guidelines

• Place the boost inductor between VBAT and SW close to device terminals with no VIAS between the device terminals and the inductor.
• Place the capacitor between VREG and VBOOST close to device terminals with no VIAS between the device terminals and capacitor.
• Place the capacitor between VBOOST/PVDD and GND close to device terminals with no VIAS between the device terminals and capacitor.
• Do not use VIAS for traces that carry high current. These include the traces for VBOOST, SW, PVDD and the speaker OUT+, OUT-.
• Use epoxy filled vias for the interior pads.
• Connect VSENSE+, VSENSE- as close as possible to the speaker.
  • VSENSE+, VSENSE- should be connected between the EMI ferrite and the speaker if EMI ferrites are used on OUT+, OUT-.
  • VSENSE+, VSENSE- should be connected between the EMI ferrite and the EMI capacitor if EMI capacitors are used. EMI ferrites must be used if EMI capacitors are used on OUT+, OUT-.
• If the analog inputs, IN+ and IN-, are:
  • used, analog input traces should be routed symmetrically for true differential performance.
  • used, do not run analog input traces parallel to digital lines.
  • used, they should be ac coupled.
  • not used, they should be shorted together.
• Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for minimum ground noise.
• Use supply decoupling capacitors as shown in Figure 50 and Figure 55 and described in Power Supply Recommendations.
• Place EMI ferrites, if used, close to the device.

10.2 Layout Example

Figure 61. TAS2552 Board Layout

10.3 Package Dimensions

The TAS2552 uses a 30-ball, 0.4 mm pitch WCSP package. The die length (D) and width (E) correspond to the package mechanical drawing at the end of the datasheet.