SCLS403I April   1998  – March 2015 SN74LV164A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: VCC = 2.5 V ± 0.2 V
    7. 6.7  Timing Requirements: VCC = 3.3 V ± 0.3 V
    8. 6.8  Timing Requirements: VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics: VCC = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics: VCC = 5 V ± 0.5 V
    12. 6.12 Noise Characteristics
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|14
  • RGY|14
  • DB|14
  • PW|14
  • DGV|14
  • NS|14
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float when disabled.

11.2 Layout Example

SN54LV164A SN74LV164A layoutex1.pngFigure 8. Layout Example