SCES502P November 2003 – June 2016 SN74AUP1G08
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
This single 2-input positive-AND gate is designed for 0.8-V to 3.6-V VCC operation and performs the Boolean function in positive logic.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm2 square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for live insertion.
INPUTS | OUTPUT Y |
|
---|---|---|
A | B | |
L | L | L |
L | H | L |
H | L | L |
H | H | H |