ZHCSFW4A November   2015  – December 2016 SN65MLVD204B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics - Driver
    7. 6.7  Electrical Characteristics - Receiver
    8. 6.8  Electrical Characteristics - BUS Input and Output
    9. 6.9  Switching Characteristics - Driver
    10. 6.10 Switching Characteristics - Receiver
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VCC < 1.5 V
      2. 8.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 8.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 8.4.4 Device Function Tables
      5. 8.4.5 Equivalent Input and Output Schematic Diagrams
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1  Supply Voltage
        2. 9.2.3.2  Supply Bypass Capacitance
        3. 9.2.3.3  Driver Input Voltage
        4. 9.2.3.4  Driver Output Voltage
        5. 9.2.3.5  Termination Resistors
        6. 9.2.3.6  Receiver Input Signal
        7. 9.2.3.7  Receiver Input Threshold (Failsafe)
        8. 9.2.3.8  Receiver Output Signal
        9. 9.2.3.9  Interconnecting Media
        10. 9.2.3.10 PCB Transmission Lines
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Detailed Description

8.1 Overview

The SN65MLVD20xB family of devices are multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30 Ω, and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of –1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other fault conditions.

8.2 Functional Block Diagram

SN65MLVD204B func_dig1_sllsen0.gif Figure 14. Block Diagram SN65MLVD200B, SN65MLVD204B
SN65MLVD204B func_dig2_sllsen0.gif Figure 15. Block Diagram SN65MLVD202B, SN65MLVD205B

8.3 Feature Description

8.3.1 Power-On-Reset

The SN65MLVD20xB family of devices operates and meets all the specified performance requirements for supply voltages in the range of 3 V to 3.6 V. When the supply voltage drops below 1.5 V (or is turning on and has not yet reached 1.5 V), power-on reset circuitry set the driver output to a high-impedance state.

8.3.2 ESD Protection

The bus terminals of the SN65MLVD20xB family possess on-chip ESD protection against ±8-kV human body model (HBM) and ±8-kV IEC61000-4-2 contact discharge. The IEC-ESD test is far more severe than the HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC model produce significantly higher discharge currents than the HBM-model.

As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results.

SN65MLVD204B hbm_app_sllsen0.gif Figure 16. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)

8.4 Device Functional Modes

8.4.1 Operation with VCC < 1.5 V

Bus pins will be high impedance under this condition.

8.4.2 Operations with 1.5 V ≤ VCC < 3 V

Operation with supply voltages in the range of 1.5 V ≤ VCC < 3 V is undefined and no specific device performance is guaranteed in this range.

8.4.3 Operation with 3 V ≤ VCC < 3.6 V

Operation with the supply voltages greater than or equal to 3 V and less than or equal to 3.6 V is normal operation.

8.4.4 Device Function Tables

Table 3. Type-1 Receiver (200B and 202B)(1)

INPUTS OUTPUT
VID = VA - VB RE R
VID ≥ 50 mV L H
–50 mV < VID < 50 mV L ?
VID ≤ –50 mV L L
X H Z
X Open Z
(1) H = high level, L = low level, Z = high impedance, X = Don't care, ? - indeterminate

Table 4. Type-2 Receiver (204B and 205B)(1)

INPUTS OUTPUT
VID = VA - VB RE R
VID ≥ 150 mV L H
50 mV < VID < 150 mV L ?
VID ≤ 50 mV L L
X H Z
X Open Z
(1) H = high level, L = low level, Z = high impedance, X = Don't care, ? - indeterminate

Table 5. Driver(1)

INPUTS ENABLE OUTPUTS
D DE A B
L H L H
H H H L
Open H L H
X Open Z Z
X L Z Z
(1) H = high level, L = low level, Z = high impedance, X = Don't care, ? - indeterminate

8.4.5 Equivalent Input and Output Schematic Diagrams

SN65MLVD204B equiv_sllsex9.gif