ZHCS601D December   2011  – May 2015 SN65HVD255 , SN65HVD256 , SN65HVD257

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Power Dissipation
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant Timeout (DTO)
      2. 9.3.2 RXD Dominant Timeout (SN65HVD257)
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Undervoltage Lockout
      5. 9.3.5 FAULT Pin (SN65HVD257)
      6. 9.3.6 Unpowered Device
      7. 9.3.7 Floating Pins
      8. 9.3.8 CAN Bus Short-Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes
      2. 9.4.2 Can Bus States
      3. 9.4.3 Normal Mode
      4. 9.4.4 Silent Mode
      5. 9.4.5 Digital Inputs and Outputs
        1. 9.4.5.1 5-V VCC Only Devices (SN65HVD255 and SN65HVD257)
        2. 9.4.5.2 5-V VCC With VRXD RXD Output Supply Devices (SN65HVD256)
        3. 9.4.5.3 5-V VCC with FAULT Open-Drain Output Device (SN65HVD257)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bus Loading, Length, and Number of Nodes
    2. 10.2 Typical Applications
      1. 10.2.1 Typical 5-V Microcontroller Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 CAN Termination
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Example: Functional Safety Using the SN65HVD257 in a Redundant Physical Layer CAN Network Topology
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical 3.3-V Microcontroller Application
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 商标
    3. 13.3 静电放电警告
    4. 13.4 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Detailed Description

9.1 Overview

The SN65HVD25x family of bus transceiver devices are compatible with the ISO 11898-2 High Speed CAN (Controller Area Network) physical layer standard. The SN65HVD25x devices are designed to interface between the differential bus lines and the CAN protocol controller at data rates up to 1 Mbps (megabits per second).

9.2 Functional Block Diagram

SN65HVD255 SN65HVD256 SN65HVD257 fbd_257_llsea2.gif
A. Pin 5 function is device dependent; NC on SN65HVD255, VRXD for RXD output level-shifting device on the SN65HVD256 device, and FAULT Output on the SN65HVD257 device.
B. RXD logic output is driven to 5-V VCC on 5-V only supply devices (SN65HVD255, SN65HVD257) and driven to VRXD on output level-shifting device (SN65HVD256).
C. RXD (Receiver) Dominant State Time Out is a device dependent option available only on the SN65HVD257 device.

9.3 Feature Description

9.3.1 TXD Dominant Timeout (DTO)

During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the timeout period tTXD_DTO. The DTO circuit timer starts on a falling edge on TXD. The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires, which frees the bus for communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is seen on TXD pin, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD dominant timeout.

NOTE

The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / tTXD_DTO.

9.3.2 RXD Dominant Timeout (SN65HVD257)

The SN65HVD257 device has a RXD dominant timeout (RXD DTO) circuit that prevents a bus stuck dominant fault from permanently driving the RXD output dominant (low) when the bus is held dominant longer than the timeout period tRXD_DTO. The RXD DTO timer starts on a falling edge on RXD (bus going dominant). If no rising edge (bus returning recessive) is seen before the timeout constant of the circuit expires (tRXD_DTO), the RXD pin returns high (recessive). The RXD output is reactivated to mirror the bus receiver output when a recessive signal is seen on the bus, clearing the RXD dominant timeout. The CAN bus pins are biased to the recessive level during a RXD DTO.

NOTE

The minimum dominant RXD time allowed by the RXD DTO limits the minimum possible received data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits for the worst case transmission, where five successive dominant bits are followed immediately by an error frame. This, along with the tRXD_DTO minimum, limits the minimum data rate. The minimum received data rate may be calculated by: Minimum Data Rate = 11 / tRXD_DTO.

9.3.3 Thermal Shutdown

If the junction temperature of the device exceeds the thermal shut down threshold, the device turns off the CAN driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the junction temperature drops below the thermal shutdown temperature of the device.

NOTE

During thermal shutdown the CAN bus drivers turn off; thus, no transmission is possible from TXD to the bus. The CAN bus pins are biased to recessive level during a thermal shutdown, and the receiver to RXD path remains operational.

9.3.4 Undervoltage Lockout

The supply pins have undervoltage detection that places the device in protected mode, which protects the bus during an undervoltage event on either the VCC or VRXD supply pins.

Table 2. Undervoltage Lockout 5-V Only Devices (SN65HVD255 and SN65HVD257)

VCC DEVICE STATE BUS OUTPUT RXD
GOOD Normal Per Device State and TXD Mirrors Bus
BAD Protected High Impedance High Impedance (3-state)

Table 3. Undervoltage Lockout 5 V and VRXD Device (SN65HVD256)

VCC VRXD DEVICE STATE BUS OUTPUT RXD
GOOD GOOD Normal Per Device State and TXD Mirrors Bus
BAD GOOD Protected High Impedance High (Recessive)
GOOD BAD Protected Recessive High Impedance (3-state)
BAD BAD Protected High Impedance High Impedance (3-state)

NOTE

After an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically resumes normal operation in 300 µs.

9.3.5 FAULT Pin (SN65HVD257)

If one or more of the faults (TXD dominant timeout, RXD dominant timeout, thermal shutdown or undervoltage lockout) occurs, the FAULT pin (open-drain) turns off, resulting in a high level when externally pulled up to VCC or I/O supply.

SN65HVD255 SN65HVD256 SN65HVD257 fault_257_llsea2.gifFigure 12. FAULT Pin Function Diagram and Application
SN65HVD255 SN65HVD256 SN65HVD257 TXD_DTO_Drawing_sllsea2.gifFigure 13. Example Timing Diagram for TXD DTO and FAULT Pin
SN65HVD255 SN65HVD256 SN65HVD257 td_RXD_DTO_llsea2.gifFigure 14. Example Timing Diagram for Devices With and Without RXD DTO and FAULT Pin

9.3.6 Unpowered Device

The SN65HVD25x device is designed to be an ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH, CANL) have extremely low leakage currents when the device is unpowered, so they will not load down the bus. This is critical if some nodes of the network will be unpowered while the rest of the of network remains in operation. The logic pins also have extremely low leakage currents when the device is unpowered to avoid loading down other circuits that may remain powered.

9.3.7 Floating Pins

The device has internal pullups and pulldowns on critical pins to place the device into known states if the pins float. The TXD pin is pulled up to VCC to force a recessive input level if the pin floats. The S pin is pulled down to GND to force the device into normal mode if the pin floats.

9.3.8 CAN Bus Short-Circuit Current Limiting

The SN65HVD25x device has several protection features that limit the short circuit current when a CAN bus line is shorted. These features include driver current limiting (dominant and recessive). The device has TXD dominant state time out to prevent permanent higher short circuit current of the dominant state during a system fault. During CAN communication, the bus switches between dominant and recessive states with the data and control fields bits; thus the short circuit current may be viewed either as the instantaneous current during each bus state or as a DC average current. For system current (power supply) and power considerations in the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at the following times:

  • Control fields with set bits
  • Bit stuffing
  • Interframe space
  • TXD dominant time out (fault case limiting)

These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits.

The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents. The average short circuit current may be calculated with Equation 1.

Equation 1. IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]

where:
IOS(AVG) is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short circuit current
IOS(SS)_DOM is the dominant steady state short circuit current

NOTE

Consider the short circuit current and possible fault cases of the network when sizing the power ratings of the termination resistance and other network components.

9.4 Device Functional Modes

Table 4. Driver Function Table

DEVICE INPUTS OUTPUTS DRIVEN BUS STATE
S(1)(2) TXD(1)(3) CANH(1) CANL(1)
All Devices L or Open L H L Dominant
H or Open Z Z Recessive
H X Z Z Recessive
(1) H = high level, L = low level, X= irrelevant, Z = common mode (recessive) bias to VCC / 2. See Figure 15 and Figure 16 for bus state and common mode bias information.
(2) Devices have an internal pulldown to GND on S pin. If S pin is open the pin will be pulled low and the device will be in normal mode.
(3) Devices have an internal pullup to VCC on TXD pin. If the TXD pin is open the pin will be pulled high and the transmitter will remain in recessive (nondriven) state.

Table 5. Receiver Function Table

DEVICE MODE CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL		 BUS STATE RXD PIN(1)
Normal or Silent VID ≥ 0.9 V Dominant L(2)
0.5 V < VID < 0.9 V ? ?
VID ≤ 0.5 V Recessive H
Open (VID ≈ 0 V) Open H
(1) H = high level, L = low level, ? = indeterminate.
(2) RXD output remains dominant (low) as long as the bus is dominant. On the SN65HVD257 device with RXD dominant timeout, when the bus has been dominant longer than the dominant timeout, tRXD_DTO, the RXD pin will return recessive (high). See RXD Dominant Timeout (SN65HVD257) for a description of behavior during receiving a bus stuck dominant condition.

9.4.1 Operating Modes

The device has two main operating modes: normal mode and silent mode. Operating mode selection is made via the S input pin.

Table 6. Operating Modes

S Pin MODE DRIVER RECEIVER RXD PIN
LOW Normal Mode Enabled (ON) Enabled (ON) Mirrors Bus State(1)
HIGH Silent Mode Disabled (OFF) Enabled (ON) Mirrors Bus State
(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

9.4.2 Can Bus States

The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD pin. A recessive bus state is when the bus is biased to VCC / 2 via the high-resistance internal input resistors RIN of the receiver, corresponding to a logic high on the TXD and RXD pins. See Figure 15 and Figure 16.

SN65HVD255 SN65HVD256 SN65HVD257 bus_states_llsea2.gifFigure 15. Bus States (Physical Bit Representation)
SN65HVD255 SN65HVD256 SN65HVD257 mode_bias_rx_llsea2.gifFigure 16. Simplified Recessive Common Mode Bias and Receiver

9.4.3 Normal Mode

Select the normal mode of device operation by setting S low. The CAN driver and receiver are fully operational and CAN communication is bidirectional. The driver is translating a digital input on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.

9.4.4 Silent Mode

Activate silent mode (receive only) by setting S high. The CAN driver is turned off while the receiver remains active and RXD outputs the received bus state.

NOTE

Silent mode may be used to implement babbling idiot protection, to ensure that the driver does not disrupt the network during a local fault. Silent mode may also be used in redundant systems to select or de-select the redundant transceiver (driver) when needed.

9.4.5 Digital Inputs and Outputs

9.4.5.1 5-V VCC Only Devices (SN65HVD255 and SN65HVD257)

The 5-V VCC device is supplied by a single 5-V rail. The digital inputs are 5-V and 3.3-V compatible. The SN65HVD255 and SN65HVD257 devices have a 5-V (VCC) level RXD output. TXD is internally pulled up to VCC and S is internally pulled down to GND.

NOTE

TXD is internally pulled up to VCC and the S pin is internally pulled down to GND. However, the internal bias may only put the device into a known state if the pins float. The internal bias may be inadequate for system-level biasing. TXD pullup strength and CAN bit timing require special consideration when the SN65HVD25x devices are used with an open-drain TXD output on the CAN controller. An adequate external pullup resistor must be used to ensure that the CAN controller output of the μP maintains adequate bit timing input to the SN65HVD25x devices.

9.4.5.2 5-V VCC With VRXD RXD Output Supply Devices (SN65HVD256)

This device is a 5-V VCC CAN transceiver with a separate supply for the RXD output, VRXD. The digital inputs are 5-V and 3.3-V compatible. The SN65HVD256 device has a VRXD level RXD output. TXD remains weakly pulled up to VCC.

NOTE

On device versions with a VRXD supply that shifts the RXD output level, the input pins of the device remain the same. TXD remains weakly pulled up to VCC internally. Thus, a small IIH current flows if the TXD input is used below VCC levels.

9.4.5.3 5-V VCC with FAULT Open-Drain Output Device (SN65HVD257)

The SN65HVD257 device has a FAULT output pin (open-drain). FAULT must be pulled up to VCC or I/O supply level through an external resistor.

NOTE

Because the FAULT output pin is open-drain, it actively pulls down when there is no fault and becomes high-impedance when a fault condition is detected. An external pullup resistor to the VCC or I/O supply of the system must be used to pull the pin high to indicate a fault to the host microprocessor. The open-drain architecture makes the fault pin compatible with 3.3-V and 5-V I/O-level systems. The pullup current, selected by the pullup resistance value, must be as low as possible while achieving the desired voltage level output in the system with margin against noise.