ZHCSB64A June   2013  – September 2014 SN6501-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
      2. 8.4.2 Operating Mode
      3. 8.4.3 Off-Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 SN6501 Drive Capability
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
          3. 9.2.2.5.3 Recommended Transformers
      3. 9.2.3 Application Curve
      4. 9.2.4 Higher Output Voltage Designs
      5. 9.2.5 Application Circuits
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

  • The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and a X5R or X7R dielectric.
  • The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 57 for a PCB layout example.
  • The connections between the device D1 and D2 pins and the transformer primary endings, and the connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum trace inductance.
  • • The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
  • The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
  • The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
  • The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range to maximize efficiency.
  • The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.

11.2 Layout Example

layoutexamplesllsea0.gifFigure 57. Layout Example of a 2-Layer Board (SN6501)