ZHCSIQ4B September   2018  – December 2018 OPA828

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      开环增益和相位与频率间的关系
      2.      失调电压漂移
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Characteristics
      2. 7.3.2  Phase-Reversal Protection
      3. 7.3.3  Electrical Overstress
      4. 7.3.4  MUX Friendly Inputs
      5. 7.3.5  Overload Power Limiter
      6. 7.3.6  Capacitive Load and Stability
      7. 7.3.7  Capacitive Load and Stability
      8. 7.3.8  Settling Time
      9. 7.3.9  Slew Rate
      10. 7.3.10 Full Power Bandwidth
      11. 7.3.11 Small Signal Response
      12. 7.3.12 Thermal Considerations
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Low Noise
      15. 7.3.15 Low Offset Voltage Drift
      16. 7.3.16 Overload Recovery
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application: SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application: Low-Pass Filter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Design Procedure

The OPA828 is configured as shown in to enable a wide input voltage range of ±10 V to be attenuated to 0 V to 5 V. The output range of the amplifier is selected based on the full scale input range of the ADS8860, a 16-bit, 1 MSPS SAR ADC. Supply rails of ±15 V are used so the amplifier can achieve linear swing across the full input range. This design allows the amplifier output to settle to 16-bits within the 290-ns acquisition time of the selected ADC.

The Analog Engineer's Calculator is used to select the resistors and capacitors used to set the signal attenuation as well as the charge bucket between the amplifier and ADC. The input and feedback resistors are chosen to provide a gain of –1/4 (for example, a 4× attenuation in an inverting configuration). VBIAS is fixed at 2 V to enable the output to swing from 0 V to 5 V. shows the simulated settling time of this circuit. To function properly the output of the amplifier must settle to within ± ½LSB before the end of the ADC's acquisition cycle. In this example using the OPA8860, the output of the amplifier must settle to within ±38.15 µV. Verror is the difference between the expected output and the actual output of the amplifier.

An 820 pF capacitor is added to the feedback to create a lowpass filter with a cutoff frequency of 194 kHz. This filter reduces the noise seen by the ADC and improves the accuracy of the system. The DC transfer function of this circuit is shown in Figure 59 and the AC response in shown in Figure 60.

See TI Precision Labs for more details and training on configuring an amplifier for ADC drive, selecting the resistors and capacitor for the charge bucket and other signal chain topics.