ZHCSIQ4B September 2018 – December 2018 OPA828
The OPA828 is configured as shown in to enable a wide input voltage range of ±10 V to be attenuated to 0 V to 5 V. The output range of the amplifier is selected based on the full scale input range of the ADS8860, a 16-bit, 1 MSPS SAR ADC. Supply rails of ±15 V are used so the amplifier can achieve linear swing across the full input range. This design allows the amplifier output to settle to 16-bits within the 290-ns acquisition time of the selected ADC.
The Analog Engineer's Calculator is used to select the resistors and capacitors used to set the signal attenuation as well as the charge bucket between the amplifier and ADC. The input and feedback resistors are chosen to provide a gain of –1/4 (for example, a 4× attenuation in an inverting configuration). VBIAS is fixed at 2 V to enable the output to swing from 0 V to 5 V. shows the simulated settling time of this circuit. To function properly the output of the amplifier must settle to within ± ½LSB before the end of the ADC's acquisition cycle. In this example using the OPA8860, the output of the amplifier must settle to within ±38.15 µV. Verror is the difference between the expected output and the actual output of the amplifier.
An 820 pF capacitor is added to the feedback to create a lowpass filter with a cutoff frequency of 194 kHz. This filter reduces the noise seen by the ADC and improves the accuracy of the system. The DC transfer function of this circuit is shown in Figure 59 and the AC response in shown in Figure 60.
See TI Precision Labs for more details and training on configuring an amplifier for ADC drive, selecting the resistors and capacitor for the charge bucket and other signal chain topics.