ZHCSOR9A November   2021  – April 2022 OPA4H014-SEP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Capacitive Load and Stability
      2. 7.3.2 Output Current Limit
      3. 7.3.3 Phase-Reversal Protection
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Performance
        1. 8.1.1.1 Basic Noise Calculations
      2. 8.1.2 Electrical Overstress
      3. 8.1.3 EMI Rejection
      4. 8.1.4 EMIRR +IN Test Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

at TA = 25°C, RL = 2 kΩ connected to midsupply, VS = ±2.25 V to ±9 V, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±30 ±120 μV
VS = ±9 V, TA = –55°C to +125°C ±220
TA = –55°C to +125°C ±4 μV/V
dVOS/dT Drift VS = ±9 V, TA = –55°C to +125°C ±0.35 ±1 μV/°C
PSRR Power-supply rejection ratio TA = –55°C to +125°C ±0.1 ±0.5 μV/V
Channel separation f = dc 0.02 µV/V
f = 100 kHz 10
INPUT BIAS CURRENT
IB Input bias current ±0.5 ±10 pA
TA = –55°C to +125°C ±3 nA
IOS Input offset current ±0.5 ±10 pA
TA = –55°C to +125°C ±1 nA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 250 nVPP
f = 0.1 Hz to 10 Hz 42 nVRMS
en Input voltage noise density f = 10 Hz 8 nV/√Hz
f = 100 Hz 5.8
f = 1 kHz 5.1
In Input current noise density f = 1 kHz 0.8 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage TA = –55°C to +125°C (V–) – 0.1 (V+) – 3.5 V
CMRR Common-mode rejection ratio VS = ±9 V,
VCM = (V–) – 0.1 V to (V+) – 3.5 V		 126 140 dB
VS = ±9 V,
VCM = (V–) – 0.1 V to (V+) – 3.5 V,
TA = –55°C to +125°C		 120
INPUT IMPEDANCE
Differential 1013 || 10 Ω || pF
Common-mode VCM = (V–) – 0.1 V to (V+) – 3.5 V 1013 || 7
OPEN-LOOP GAIN
AOL Open-loop voltage gain VO = (V–) + 0.35 V to (V+) – 0.35 V,
RL = 10 kΩ		 120 126 dB
VO = (V–) + 0.35 V to (V+) – 0.35 V 114 126
VO = (V–) + 0.35 V to (V+) – 0.35 V,
TA = –55°C to +125°C		 108
FREQUENCY RESPONSE
BW Gain bandwidth product 11 MHz
SR Slew rate 20 V/μs
Settling time 12 bits 10-V step, gain = +1 0.88 μs
16 bits 10-V step, gain = +1 1.6
THD+N Total harmonic distortion and noise f = 1 kHz, gain = +1, VO = 3.5 VRMS 0.00005%
Overload recovery time 600 ns
OUTPUT
Output swing from rail RL = 10 kΩ, AOL ≥ 108 dB (V–) + 0.2 (V+) – 0.2 V
AOL ≥ 108 dB (V–) + 0.35 (V+) – 0.35
ISC Short-circuit current Source 36 mA
Sink –30
CLOAD Capacitive load drive See Figure 6-17 and Figure 6-18
ZO Open-loop output impedance f = 1 MHz, IO = 0 mA 16 Ω
POWER SUPPLY
IQ Quiescent current (per amplifier) IO = 0 mA 1.8 2 mA
TA = –55°C to +125°C 2.7