ZHCSMO3C June   2020  – April 2021 OPA2863 , OPA863

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: OPA863
    5. 7.5  Thermal Information: OPA2863
    6. 7.6  Electrical Characteristics: 10 V
    7. 7.7  Electrical Characteristics: 3 V
    8. 7.8  Typical Characteristics: VS = 10 V
    9. 7.9  Typical Characteristics: VS = 3 V
    10. 7.10 Typical Characteristics: VS = 3 V to 10 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
        1. 8.3.2.1 Overload Power Limit
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 Split-Supply Operation (±1.35 V to ±6.3 V)
      3. 8.4.3 Single-Supply Operation (2.7 V to 12.6 V)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Amplifier Gain Configurations
    2. 9.2 Low-Side Current Sensing
      1. 9.2.1 Design Requirements
    3. 9.3 Transimpedance Amplifier
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 Low-Power SAR ADC Driver and Reference Buffer
    5. 9.5 Front-End Gain and Filtering
    6. 9.6 Clamp-On Ultrasonic Flow Meter
    7. 9.7 Variable Reference Generator Using MDAC
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Overload Power Limit

The OPAx863 devices include overload power limiting which limits the increase in device quiescent current with output saturated to either of the supplies. Typically, when an amplifier's output saturates, its two inputs are pulled apart which may enable the slew boost circuit. The input differential voltage is an error voltage in negative feedback, which the amplifier core nullifies by engaging the slew boost circuit and driving the output stage deeper into saturation. Once the input to an amplifier attains a value large enough to saturate its output, any further increase in this input excitation results in a finite input differential voltage. As the output stage transistor is pushed deeper into saturation, its hFE (base-to-collector current gain) drops with increase in its base and collector current, increasing the device quiescent current. This may cause a catastrophic failure in multi-channel, high-gain, high-density front-end designs and reduce operating lifetime in portable battery powered systems. The OPAx863 devices overload power limiting includes an intelligent output saturation detection circuit which limits the device's quiescent current to 2.2-mA per channel under DC overload conditions. This increase in quiescent current is smaller with AC input or output and output saturation duration for only a fraction of the overall signal time period. Table 8-1 compares the increase in quiescent current with 50 mV input overdrive for OPAx863 devices and other voltage feedback amplifiers without overload power limit.

Table 8-1 Quiescent Current with Saturated Outputs
Device Input Differential Voltage Quiescent Current Increase in IQ from steady-state condition
OPAx863 with overload power limit 50 mV 1.1 mA 1.57x
Competitor amplifier without overload power limit 50 mV 1.96 mA 3.43x