ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | I(OHmax) = –1 mA(1) | 2.2 V | VCC – 0.25 | VCC | V |
I(OHmax) = –3 mA(2) | VCC – 0.60 | VCC | ||||
I(OHmax) = –2 mA(1) | 3.0 V | VCC – 0.25 | VCC | |||
I(OHmax) = –6 mA(2) | VCC – 0.60 | VCC | ||||
VOL | Low-level output voltage | I(OLmax) = 1 mA(1) | 2.2 V | VSS | VSS + 0.25 | V |
I(OLmax) = 3 mA(2) | VSS | VSS + 0.60 | ||||
I(OLmax) = 2 mA(1) | 3.0 V | VSS | VSS + 0.25 | |||
I(OLmax) = 6 mA(2) | VSS | VSS + 0.60 | ||||
fPx.y | Port output frequency (with RC load)(5) | VCORE = 1.2 V, CL = 20 pF, RL(3)(4) | 1.62 V | 12 | MHz | |
2.2 V | 12 | |||||
3.0 V | 12 | |||||
dPx.y | Port output duty cycle (with RC load) | VCORE = 1.2 V, CL = 20 pF, RL(3)(4) | 1.62 V | 40% | 60% | |
2.2 V | 40% | 60% | ||||
3.0 V | 45% | 55% | ||||
fPort_CLK | Clock output frequency(5) | VCORE = 1.2 V, CL = 20 pF(4) | 1.62 V | 12 | MHz | |
2.2 V | 12 | |||||
3.0 V | 12 | |||||
dPort_CLK | Clock output duty cycle | VCORE = 1.2 V, CL = 20 pF(4) | 1.62 V | 40% | 60% | |
2.2 V | 40% | 60% | ||||
3.0 V | 45% | 55% | ||||
trise,dig | Port output rise time, digital only port pins | CL = 20 pF(6) | 1.62 V | 8 | ns | |
2.2 V | 5 | |||||
3.0 V | 3 | |||||
tfall,dig | Port output fall time, digital only port pins | CL = 20 pF(7) | 1.62 V | 8 | ns | |
2.2 V | 5 | |||||
3.0 V | 3 | |||||
trise,ana | Port output rise time, port pins with shared analog functions | CL = 20 pF(6) | 1.62 V | 8 | ns | |
2.2 V | 5 | |||||
3.0 V | 3 | |||||
tfall,ana | Port output fall time, port pins with shared analog functions | CL = 20 pF(7) | 1.62 V | 8 | ns | |
2.2 V | 5 | |||||
3.0 V | 4 |
Table 5-25 lists the output characteristics of the high-drive digital I/Os.
See Figure 5-23, Figure 5-24, Figure 5-25, and Figure 5-26 for the typical characteristics graphs.