ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
PARAMETER | ORIGINAL OPERATING MODE | FINAL OPERATING MODE | TEST CONDITIONS | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
tOFF_AMLDO0 | Power Off | AM_LDO_VCORE0 | From VCC reaching 1.71 V to start of user application code | 6 | ms | |
tAMLDO0_AMDCDC0 | AM_LDO_VCORE0 | AM_DCDC_VCORE0 | Transition from AM_LDO_VCORE0 to AM_DCDC_VCORE0
MCLK frequency = 24 MHz |
20 | 30 | µs |
tAMDCDC0_AMLDO0 | AM_DCDC_VCORE0 | AM_LDO_VCORE0 | Transition from AM_DCDC_VCORE0 to AM_LDO_VCORE0
MCLK frequency = 24 MHz |
10 | 15 | µs |
tAMLDO0_AMLF0 | AM_LDO_VCORE0 | AM_LF_VCORE0 | Transition from AM_LDO_VCORE0 to AM_LF_VCORE0
SELM = 2, REFO frequency = 128 kHz |
90 | 100 | µs |
tAMLF0_AMLDO0 | AM_LF_VCORE0 | AM_LDO_VCORE0 | Transition from AM_LF_VCORE0 to AM_LDO_VCORE0
SELM = 2, REFO frequency = 128 kHz |
50 | 60 | µs |
Table 5-5 lists the latencies required to change between different active and LPM0 modes.