5.11 Current Consumption in DC/DC-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)(4)(5)
PARAMETER |
EXECUTION MEMORY |
VCC |
MCLK = 1 MHz |
MCLK = 8 MHz |
MCLK = 16 MHz |
MCLK = 24 MHz |
UNIT |
TYP |
MAX |
TYP |
MAX |
TYP |
MAX |
TYP |
MAX |
IAM_DCDC_VCORE0,Flash(6)(7)(9) |
Flash |
3.0 V |
580 |
1050 |
1280 |
1850 |
1970 |
2650 |
2390 |
3200 |
µA |
IAM_DCDC_VCORE0,SRAM(8) |
SRAM |
3.0 V |
550 |
1000 |
1040 |
1750 |
1600 |
2350 |
2170 |
3000 |
µA |
(1) MCLK sourced by DCO.
(2) Current measured into VCC.
(3) All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
(4) All SRAM banks kept active.
(5) All peripherals are inactive.
(6) Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
(7) Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8) Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
(9) Flash instruction and data buffers are enabled (BUFI = BUFD = 1).