ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
Figure 6-20 and Figure 6-21 show the port schematics. Table 6-82 lists the settings to select the pin function.
PIN NAME (PJ.x) | x | FUNCTION | CONTROL BITS OR SIGNALS (1) | |||||
---|---|---|---|---|---|---|---|---|
PJDIR.x | PJSEL1.1 | PJSEL0.1 | PJSEL1.0 | PJSEL0.0 | LFXT BYPASS | |||
PJ.0/LFXIN | 0 | PJ.0 (I/O) | I: 0; O: 1 | X | X | 0 | 0 | X |
N/A | 0 | X | X | 1 | X | X | ||
DVSS | 1 | |||||||
LFXIN crystal mode (3) | X | X | X | 0 | 1 | 0 | ||
LFXIN bypass mode (3) | X | X | X | 0 | 1 | 1 | ||
PJ.1/LFXOUT | 1 | PJ.1 (I/O) | I: 0; O: 1 | 0 | 0 | 0 | 0 | 0 |
1 | X | |||||||
X | X | 1(4) | ||||||
N/A | 0 | see(2) | see(2) | 0 | 0 | 0 | ||
1 | X | |||||||
X | X | 1(4) | ||||||
DVSS | 1 | see(2) | see(2) | 0 | 0 | 0 | ||
1 | X | |||||||
X | X | 1(4) | ||||||
LFXOUT crystal mode (3) | X | X | X | 0 | 1 | 0 |