ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
Pin schematic: see Figure 6-8
Table 6-63 lists the settings to select the pin function.
PIN NAME (P3.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | |||
---|---|---|---|---|---|---|
P3DIR.x | P3SEL1.x | P3SEL0.x | P3MAPx | |||
P3.0/PM_UCA2STE/L7 | 0 | P3.0 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA2STE | X(2) | 0 | 1 | default | ||
L7(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.1/PM_UCA2CLK/L6 | 1 | P3.1 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA2CLK | X(2) | 0 | 1 | default | ||
L6(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.2/PM_UCA2RXD/PM_UCA2SOMI/L5 | 2 | P3.2 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA2RXD/UCA2SOMI | X(2) | 0 | 1 | default | ||
L5(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.3/PM_UCA2TXD/PM_UCA2SIMO/L4 | 3 | P3.3 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA2TXD/UCA2SIMO | X(2) | 0 | 1 | default | ||
L4(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.4/PM_UCB2STE/L3 | 4 | P3.4 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCB2STE | X(3) | 0 | 1 | default | ||
L3(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.5/PM_UCB2CLK/L2 | 5 | P3.5 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCB2CLK | X(3) | 0 | 1 | default | ||
L2(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.6/PM_UCB2SIMO/PM_UCB2SDA/L1 | 6 | P3.6 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCB2SIMO/UCB2SDA | X(3) | 0 | 1 | default | ||
L1(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P3.7/PM_UCB2SOMI/PM_UCB2SCL/L0 | 7 | P3.7 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCB2SOMI/UCB2SCL | X(3) | 0 | 1 | default | ||
L0(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 |