ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
Pin schematic: see Figure 6-8
Table 6-62 lists the settings to select the pin function.
PIN NAME (P2.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | |||
---|---|---|---|---|---|---|
P2DIR.x | P2SEL1.x | P2SEL0.x | P2MAPx | |||
P2.0/PM_UCA1STE/L11 | 0 | P2.0 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA1STE | X(2) | 0 | 1 | default | ||
L11(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P2.1/PM_UCA1CLK/L10 | 1 | P2.1 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA1CLK | X(2) | 0 | 1 | default | ||
L10(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P2.2/PM_UCA1RXD/PM_UCA1SOMI/L9 | 2 | P2.2 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA1RXD/UCA1SOMI | X(2) | 0 | 1 | default | ||
L9(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 | |||||
P2.3/PM_UCA1TXD/PM_UCA1SIMO/L8 | 3 | P2.3 (I/O) | I: 0; O: 1 | 0 | 0 | X |
UCA1TXD/UCA1SIMO | X(2) | 0 | 1 | default | ||
L8(4) | X | 1 | 0 | X | ||
N/A | 0 | 1 | 1 | X | ||
DVSS | 1 |