ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
Figure 6-8 shows the port schematic. Table 6-61 lists the settings to select the pin function.
PIN NAME (P1.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | ||
---|---|---|---|---|---|
P1DIR.x | P1SEL1.x | P1SEL0.x | |||
P1.0/UCA0STE/L19 | 0 | P1.0 (I/O) | I: 0; O: 1 | 0 | 0 |
UCA0STE | X(2) | 0 | 1 | ||
L19(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.1/UCA0CLK/L18 | 1 | P1.1 (I/O) | I: 0; O: 1 | 0 | 0 |
UCA0CLK | X(2) | 0 | 1 | ||
L18(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.2/UCA0RXD/UCA0SOMI/L17 | 2 | P1.2 (I/O) | I: 0; O: 1 | 0 | 0 |
UCA0RXD/UCA0SOMI | X(2) | 0 | 1 | ||
L17(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.3/UCA0TXD/UCA0SIMO/L16 | 3 | P1.3 (I/O) | I: 0; O: 1 | 0 | 0 |
UCA0TXD/UCA0SIMO | X(2) | 0 | 1 | ||
L16(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.4/UCB0STE/L15 | 4 | P1.4 (I/O) | I: 0; O: 1 | 0 | 0 |
UCB0STE | X(3) | 0 | 1 | ||
L15(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.5/UCB0CLK/L14 | 5 | P1.5 (I/O) | I: 0; O: 1 | 0 | 0 |
UCB0CLK | X(3) | 0 | 1 | ||
L14(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.6/UCB0SIMO/UCB0SDA/L13 | 6 | P1.6 (I/O) | I: 0; O: 1 | 0 | 0 |
UCB0SIMO/UCB0SDA | X(3) | 0 | 1 | ||
L13(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 | ||||
P1.7/UCB0SOMI/UCB0SCL/L12 | 7 | P1.7 (I/O) | I: 0; O: 1 | 0 | 0 |
UCB0SOMI/UCB0SCL | X(3) | 0 | 1 | ||
L12(4) | X | 1 | 0 | ||
N/A | 0 | 1 | 1 | ||
DVSS | 1 |