The device supports both 4-pin JTAG and the 2-pin SWD modes of operation. The device is compatible with all standard Cortex-M4 debuggers available in the market today. The debug logic in the device has been designed to remain minimally intrusive to the application state. In low-power modes, the user can enable the debugger to override the state of the PSS, thereby gaining access to debug and trace features.
In 2-pin SWD mode, the TDO pin can be used to export serial wire trace output (SWO) data. In addition, the TDI and TDO pins of the device can be reassigned as user I/Os. See Section 6.12.24 and Section 6.12.25 for more details.
If the device has activated debug security, debugger accesses into the device is disabled. The debugger, however, can still detect the run or halt state of the CPU. More control of and visibility into the device is possible only after initiating a mass erase of the device flash contents.