ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
The PCM controls the operating modes of the device and the switching between the modes. Mode selection is controlled by the application, which can choose modes to meet its power and performance requirements. Table 6-43 lists the operating modes of the device.
OPERATING MODE | DESCRIPTION |
---|---|
AM_LDO_VCORE0 | LDO-based active mode, medium performance, core voltage level 0 |
LPM0_LDO_VCORE0 | Same as AM_LDO_VCORE0, except that CPU is off (no code execution) |
AM_DCDC_VCORE0 | DC/DC-based active mode, medium performance, core voltage level 0 |
LPM0_DCDC_VCORE0 | Same as AM_DCDC_VCORE0, except that CPU is off (no code execution) |
AM_LF_VCORE0 | LDO-based low-frequency active mode, core voltage level 0 |
LPM0_LF_VCORE0 | Same as AM_LF_VCORE0, except that CPU is off (no code execution) |
LPM3_VCORE0 | LDO-based low-power mode with full state retention, core voltage level 0. In addition to RTC_C and WDT_A, other peripherals can be operational with an external or internal low-frequency clocks up to 128 kHz. Table 6-44 lists the peripherals that are available in this mode. |
LPM4_VCORE0 | LDO-based low-power mode with full state retention, core voltage level 0. Peripherals can be operational out of external clocks up to 128 kHz. Table 6-44 lists the peripherals that are available in this mode. |
LPM3.5 | LDO-based low-power mode, core voltage level 0, no retention of peripheral registers, RTC_C and WDT_A can be active. |
LPM4.5 | Core voltage turned off, wake up only through the reset pin or wake-up capable I/Os |