ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
Table 6-40 lists the various interrupt sources and their connection to the NVIC inputs.
NOTE
Some sources have multiple interrupt conditions. In this case, the appropriate interrupt status or flag register of the source must be examined to differentiate between the generating conditions.
NVIC INTERRUPT INPUT | SOURCE | FLAGS IN SOURCE |
---|---|---|
INTISR[0] | PSS (2) | |
INTISR[1] | CS (2) | |
INTISR[2] | PCM (2) | |
INTISR[3] | WDT_A | |
INTISR[4] | FPU_INT (3) | Combined interrupt from flags in the FPSCR (part of Cortex-M4 FPU) |
INTISR[5] | FLCTL_A | FLCTL_A interrupt flags |
INTISR[6] | COMP_E0 | Comparator_E0 interrupt flags |
INTISR[7] | COMP_E1 | Comparator_E1 interrupt flags |
INTISR[8] | Timer_A0 | TA0CCTL0.CCIFG |
INTISR[9] | Timer_A0 | TA0CCTLx.CCIFG (x = 1 to 4), TA0CTL.TAIFG |
INTISR[10] | Timer_A1 | TA1CCTL0.CCIFG |
INTISR[11] | Timer_A1 | TA1CCTLx.CCIFG (x = 1 to 4), TA1CTL.TAIFG |
INTISR[12] | Timer_A2 | TA2CCTL0.CCIFG |
INTISR[13] | Timer_A2 | TA2CCTLx.CCIFG (x = 1 to 4), TA2CTL.TAIFG |
INTISR[14] | Timer_A3 | TA3CCTL0.CCIFG |
INTISR[15] | Timer_A3 | TA3CCTLx.CCIFG (x = 1 to 4), TA3CTL.TAIFG |
INTISR[16] | eUSCI_A0 | UART or SPI mode TX, RX, and status flags |
INTISR[17] | eUSCI_A1 | UART or SPI mode TX, RX, and status flags |
INTISR[18] | eUSCI_A2 | UART or SPI mode TX, RX, and status flags |
INTISR[19] | eUSCI_A3 | UART or SPI mode TX, RX, and status flags |
INTISR[20] | eUSCI_B0 | SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode) |
INTISR[21] | eUSCI_B1 | SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode) |
INTISR[22] | eUSCI_B2 | SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode) |
INTISR[23] | eUSCI_B3 | SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode) |
INTISR[24] | Precision ADC | IFG[0-31], LOIFG, INIFG, HIIFG, RDYIFG, OVIFG, TOVIFG |
INTISR[25] | Timer32_INT1 | Timer32 interrupt for Timer 1 |
INTISR[26] | Timer32_INT2 | Timer32 interrupt for Timer 2 |
INTISR[27] | Timer32_INTC | Timer32 combined interrupt |
INTISR[28] | AES256 | AESRDYIFG |
INTISR[29] | RTC_C | OFIFG, RDYIFG, TEVIFG, AIFG, RT0PSIFG, RT1PSIFG |
INTISR[30] | DMA_ERR | DMA error interrupt |
INTISR[31] | DMA_INT3 | DMA completion interrupt 3 |
INTISR[32] | DMA_INT2 | DMA completion interrupt 2 |
INTISR[33] | DMA_INT1 | DMA completion interrupt 1 |
INTISR[34] | DMA_INT0(1) | DMA completion interrupt0 |
INTISR[35] | I/O Port P1 | P1IFG.x (x = 0 to 7) |
INTISR[36] | I/O Port P2 | P2IFG.x (x = 0 to 7) |
INTISR[37] | I/O Port P3 | P3IFG.x (x = 0 to 7) |
INTISR[38] | I/O Port P4 | P4IFG.x (x = 0 to 7) |
INTISR[39] | I/O Port P5 | P5IFG.x (x = 0 to 7) |
INTISR[40] | I/O Port P6 | P6IFG.x (x = 0 to 7) |
INTISR[41] | LCD_F | LCD interrupt flags |
INTISR[42] | Reserved | |
INTISR[43] | Reserved | |
INTISR[44] | Reserved | |
INTISR[45] | Reserved | |
INTISR[46] | Reserved | |
INTISR[47] | Reserved | |
INTISR[48] | Reserved | |
INTISR[49] | Reserved | |
INTISR[50] | Reserved | |
INTISR[51] | Reserved | |
INTISR[52] | Reserved | |
INTISR[53] | Reserved | |
INTISR[54] | Reserved | |
INTISR[55] | Reserved | |
INTISR[56] | Reserved | |
INTISR[57] | Reserved | |
INTISR[58] | Reserved | |
INTISR[59] | Reserved | |
INTISR[60] | Reserved | |
INTISR[61] | Reserved | |
INTISR[62] | Reserved | |
INTISR[63] | Reserved |
NOTE
The Interrupt Service Routine (ISR) must ensure that the relevant interrupt flag in the source peripheral is cleared before returning from the ISR. If the flag is not cleared, the same interrupt may be incorrectly triggered again as a new event, even though the event has already been processed by the ISR. As there may be a few cycles of delay between the execution of the write command and the actual write reflecting in the interrupt flag register of the peripheral, TI recommends that the application carry out the write and wait for a few cycles before exiting the ISR. Alternatively, the application can read the flag to ensure that it is cleared before exiting the ISR.