ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
Table 4-3 describes the signals for all device variants and package options.
FUNCTION | SIGNAL NAME | SIGNAL NO.(2) | SIGNAL TYPE(1) | DESCRIPTION | |
---|---|---|---|---|---|
PZ | RGC | ||||
ADC | A0 | 69 | 44 | I | ADC analog input A0 |
A1 | 68 | 43 | I | ADC analog input A1 | |
A2 | 67 | 42 | I | ADC analog input A2 | |
A3 | 66 | 41 | I | ADC analog input A3 | |
A4 | 65 | 40 | I | ADC analog input A4 | |
A5 | 64 | 39 | I | ADC analog input A5 | |
A6 | 63 | 38 | I | ADC analog input A6 | |
A7 | 62 | 37 | I | ADC analog input A7 | |
A8 | 61 | 36 | I | ADC analog input A8 | |
A9 | 60 | 35 | I | ADC analog input A9 | |
A10 | 59 | 34 | I | ADC analog input A10 | |
A11 | 58 | 33 | I | ADC analog input A11 | |
A12 | 57 | N/A | I | ADC analog input A12 | |
A13 | 56 | N/A | I | ADC analog input A13 | |
A14 | 55 | N/A | I | ADC analog input A14 | |
A15 | 54 | N/A | I | ADC analog input A15 | |
A16 | 53 | N/A | I | ADC analog input A16 | |
A17 | 52 | N/A | I | ADC analog input A17 | |
A18 | 51 | N/A | I | ADC analog input A18 | |
A19 | 50 | N/A | I | ADC analog input A19 | |
A20 | 49 | N/A | I | ADC analog input A20 | |
A21 | 48 | N/A | I | ADC analog input A21 | |
A22 | 47 | N/A | I | ADC analog input A22 | |
A23 | 46 | N/A | I | ADC analog input A23 | |
Clock | ACLK | 58 | 33 | O | ACLK clock output |
DCOR | 44 | 31 | – | DCO external resistor pin | |
HFXIN | 86 | 55 | I | Input for high-frequency crystal oscillator HFXT | |
HFXOUT | 85 | 54 | O | Output for high-frequency crystal oscillator HFXT | |
HSMCLK | 60 | 35 | O | HSMCLK clock output | |
LFXIN | 41 | 28 | I | Input for low-frequency crystal oscillator LFXT | |
LFXOUT | 42 | 29 | O | Output of low-frequency crystal oscillator LFXT | |
MCLK | 59 | 34 | O | MCLK clock output | |
Comparator | C0.0 | 31 | 18 | I | Comparator_E0 input 0 |
C0.1 | 30 | 17 | I | Comparator_E0 input 1 | |
C0.2 | 29 | N/A | I | Comparator_E0 input 2 | |
C0.3 | 28 | N/A | I | Comparator_E0 input 3 | |
C0.4 | 27 | N/A | I | Comparator_E0 input 4 | |
C0.5 | 26 | N/A | I | Comparator_E0 input 5 | |
C0.6 | 25 | N/A | I | Comparator_E0 input 6 | |
C0.7 | 24 | N/A | I | Comparator_E0 input 7 | |
C1.0 | 81 | 50 | I | Comparator_E1 input 0 | |
C1.1 | 80 | 49 | I | Comparator_E1 input 1 | |
C1.2 | 79 | N/A | I | Comparator_E1 input 2 | |
C1.3 | 78 | N/A | I | Comparator_E1 input 3 | |
C1.4 | 77 | N/A | I | Comparator_E1 input 4 | |
C1.5 | 76 | N/A | I | Comparator_E1 input 5 | |
C1.6 | 71 | 46 | I | Comparator_E1 input 6 | |
C1.7 | 70 | 45 | I | Comparator_E1 input 7 | |
LCD(4) | L0 | 39 | N/A | O | LCD drive pin 0; either segment or common output |
L1 | 38 | N/A | O | LCD drive pin 1; either segment or common output | |
L2 | 37 | N/A | O | LCD drive pin 2; either segment or common output | |
L3 | 36 | N/A | O | LCD drive pin 3; either segment or common output | |
L4 | 35 | N/A | O | LCD drive pin 4; either segment or common output | |
L5 | 34 | N/A | O | LCD drive pin 5; either segment or common output | |
L6 | 33 | N/A | O | LCD drive pin 6; either segment or common output | |
L7 | 32 | N/A | O | LCD drive pin 7; either segment or common output | |
L8 | 19 | N/A | O | LCD drive pin 8; either segment or common output | |
L9 | 18 | N/A | O | LCD drive pin 9; either segment or common output | |
L10 | 17 | N/A | O | LCD drive pin 10; either segment or common output | |
L11 | 16 | N/A | O | LCD drive pin 11; either segment or common output | |
L12(7) | 11, 57 | N/A | O | LCD drive pin 12; either segment or common output | |
L13(7) | 10, 56 | N/A | O | LCD drive pin 13; either segment or common output | |
L14(7) | 9, 55 | N/A | O | LCD drive pin 14; either segment or common output | |
L15(7) | 8, 54 | N/A | O | LCD drive pin 15; either segment or common output | |
L16(7) | 7, 53 | N/A | O | LCD drive pin 16; either segment or common output | |
L17(7) | 6, 52 | N/A | O | LCD drive pin 17; either segment or common output | |
L18(7) | 5, 51 | N/A | O | LCD drive pin 18; either segment or common output | |
L19(7) | 4, 50 | N/A | O | LCD drive pin 19; either segment or common output | |
L20 | 23 | N/A | O | LCD drive pin 20; either segment or common output | |
L21 | 22 | N/A | O | LCD drive pin 21; either segment or common output | |
L22 | 21 | N/A | O | LCD drive pin 22; either segment or common output | |
L23 | 20 | N/A | O | LCD drive pin 23; either segment or common output | |
L24 | 79 | N/A | O | LCD drive pin 24; either segment or common output | |
LCD(4) (continued) | L25 | 78 | N/A | O | LCD drive pin 25; either segment or common output |
L26 | 77 | N/A | O | LCD drive pin 26; either segment or common output | |
L27 | 76 | N/A | O | LCD drive pin 27; either segment or common output | |
L28 | 29 | N/A | O | LCD drive pin 28; either segment or common output | |
L29 | 28 | N/A | O | LCD drive pin 29; either segment or common output | |
L30 | 27 | N/A | O | LCD drive pin 30; either segment or common output | |
L31 | 26 | N/A | O | LCD drive pin 31; either segment or common output | |
L32 | 75 | N/A | O | LCD drive pin 32; either segment or common output | |
L33 | 74 | N/A | O | LCD drive pin 33; either segment or common output | |
L34 | 25 | N/A | O | LCD drive pin 34; either segment or common output | |
L35 | 24 | N/A | O | LCD drive pin 35; either segment or common output | |
L36 | 3 | N/A | O | LCD drive pin 36; either segment or common output | |
L37 | 2 | N/A | O | LCD drive pin 37; either segment or common output | |
L38 | 1 | N/A | O | LCD drive pin 38; either segment or common output | |
L39 | 100 | N/A | O | LCD drive pin 39; either segment or common output | |
L40 | 99 | N/A | O | LCD drive pin 40; either segment or common output | |
L41 | 98 | N/A | O | LCD drive pin 41; either segment or common output | |
L42 | 97 | N/A | O | LCD drive pin 42; either segment or common output | |
L43 | 96 | N/A | O | LCD drive pin 43; either segment or common output | |
L44 | 49 | N/A | O | LCD drive pin 44; either segment or common output | |
L45 | 48 | N/A | O | LCD drive pin 45; either segment or common output | |
L46 | 47 | N/A | O | LCD drive pin 46; either segment or common output | |
L47 | 46 | N/A | O | LCD drive pin 47; either segment or common output | |
R03 | 88 | N/A | I | Input port of fourth most positive analog LCD voltage V4 in External Bias Mode. | |
R13 | 89 | N/A | I | Input port of fourth most positive analog LCD voltage V3 in External Bias Mode. | |
R23 | 90 | N/A | I | Input port of fourth most positive analog LCD voltage V2 in External Bias Mode. | |
Debug | SWCLKTCK | 95 | 64 | I | Serial wire clock input (SWCLK)/JTAG clock input (TCK) |
SWDIOTMS | 94 | 63 | I/O | Serial wire data input/output (SWDIO)/JTAG test mode select (TMS) | |
SWO | 93 | 62 | O | Serial wire trace output | |
TDI | 92 | 61 | I | JTAG test data input | |
TDO | 93 | 62 | O | JTAG test data output | |
GPIO (P1) | P1.0 | 4 | 1 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability |
P1.1 | 5 | 2 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P1.2 | 6 | 3 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P1.3 | 7 | 4 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P1.4 | 8 | 5 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability | |
P1.5 | 9 | 6 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability | |
P1.6 | 10 | 7 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P1.7 | 11 | 8 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
GPIO (P2) | P2.0 | 16 | 13 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high-drive operation with a drive capability of up to 20 mA. |
P2.1 | 17 | 14 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high-drive operation with a drive capability of up to 20 mA. | |
P2.2 | 18 | 15 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high-drive operation with a drive capability of up to 20 mA. | |
P2.3 | 19 | 16 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function. This I/O can be configured for high-drive operation with a drive capability of up to 20 mA. | |
P2.4 | 20 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P2.5 | 21 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P2.6 | 22 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P2.7 | 23 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
GPIO (P3) | P3.0 | 32 | 19 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability, and with reconfigurable port mapping secondary function |
P3.1 | 33 | 20 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P3.2 | 34 | 21 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P3.3 | 35 | 22 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P3.4 | 36 | 23 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability, and with reconfigurable port mapping secondary function | |
P3.5 | 37 | 24 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability, and with reconfigurable port mapping secondary function | |
P3.6 | 38 | 25 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
P3.7 | 39 | 26 | I/O | General-purpose digital I/O with port interrupt and wake-up capability and with reconfigurable port mapping secondary function | |
GPIO (P4) | P4.0 | 56 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability |
P4.1 | 57 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P4.2 | 58 | 33 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P4.3 | 59 | 34 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P4.4 | 60 | 35 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P4.5 | 61 | 36 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P4.6 | 62 | 37 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P4.7 | 63 | 38 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
GPIO (P5) | P5.0 | 64 | 39 | I/O | General-purpose digital I/O with port interrupt and wake-up capability |
P5.1 | 65 | 40 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P5.2 | 66 | 41 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P5.3 | 67 | 42 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P5.4 | 68 | 43 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P5.5 | 69 | 44 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P5.6 | 70 | 45 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P5.7 | 71 | 46 | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
GPIO (P6) | P6.0 | 54 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability |
P6.1 | 55 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P6.2 | 76 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P6.3 | 77 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P6.4 | 78 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P6.5 | 79 | N/A | I/O | General-purpose digital I/O with port interrupt and wake-up capability | |
P6.6 | 80 | 49 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability | |
P6.7 | 81 | 50 | I/O | General-purpose digital I/O with port interrupt, wake-up, and glitch filtering capability | |
GPIO (P7) | P7.0 | 88 | 57 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) |
P7.1 | 89 | 58 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
P7.2 | 90 | 59 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
P7.3 | 91 | 60 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
P7.4 | 26 | N/A | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
P7.5 | 27 | N/A | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
P7.6 | 28 | N/A | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
P7.7 | 29 | N/A | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function (RD) | |
GPIO (P8) | P8.0 | 30 | 17 | I/O | General-purpose digital I/O |
P8.1 | 31 | 18 | I/O | General-purpose digital I/O | |
P8.2 | 46 | N/A | I/O | General-purpose digital I/O | |
P8.3 | 47 | N/A | I/O | General-purpose digital I/O | |
P8.4 | 48 | N/A | I/O | General-purpose digital I/O | |
P8.5 | 49 | N/A | I/O | General-purpose digital I/O | |
P8.6 | 50 | N/A | I/O | General-purpose digital I/O | |
P8.7 | 51 | N/A | I/O | General-purpose digital I/O | |
GPIO (P9) | P9.0 | 52 | N/A | I/O | General-purpose digital I/O |
P9.1 | 53 | N/A | I/O | General-purpose digital I/O | |
P9.2 | 74 | N/A | I/O | General-purpose digital I/O | |
P9.3 | 75 | N/A | I/O | General-purpose digital I/O | |
P9.4 | 96 | N/A | I/O | General-purpose digital I/O | |
P9.5 | 97 | N/A | I/O | General-purpose digital I/O | |
P9.6 | 98 | N/A | I/O | General-purpose digital I/O | |
P9.7 | 99 | N/A | I/O | General-purpose digital I/O | |
GPIO (P10) | P10.0 | 100 | N/A | I/O | General-purpose digital I/O |
P10.1 | 1 | N/A | I/O | General-purpose digital I/O | |
P10.2 | 2 | N/A | I/O | General-purpose digital I/O | |
P10.3 | 3 | N/A | I/O | General-purpose digital I/O | |
P10.4 | 24 | N/A | I/O | General-purpose digital I/O | |
P10.5 | 25 | N/A | I/O | General-purpose digital I/O | |
GPIO (PJ) | PJ.0 | 41 | 28 | I/O | General-purpose digital I/O |
PJ.1 | 42 | 29 | I/O | General-purpose digital I/O | |
PJ.2 | 85 | 54 | I/O | General-purpose digital I/O | |
PJ.3 | 86 | 55 | I/O | General-purpose digital I/O | |
PJ.4 | 92 | 61 | I/O | General-purpose digital I/O | |
PJ.5 | 93 | 62 | I/O | General-purpose digital I/O | |
I2C | UCB0SCL | 11 | 8 | I/O | I2C clock – eUSCI_B0 I2C mode |
UCB0SDA | 10 | 7 | I/O | I2C data – eUSCI_B0 I2C mode | |
UCB1SCL | 79 | N/A | I/O | I2C clock – eUSCI_B1 I2C mode | |
UCB1SDA | 78 | N/A | I/O | I2C data – eUSCI_B1 I2C mode | |
UCB3SCL | 3 | N/A | I/O | I2C clock – eUSCI_B3 I2C mode | |
UCB3SCL | 81 | 50 | I/O | I2C clock – eUSCI_B3 I2C mode | |
UCB3SDA | 2 | N/A | I/O | I2C data – eUSCI_B3 I2C mode | |
UCB3SDA | 80 | 49 | I/O | I2C data – eUSCI_B3 I2C mode | |
Port Mapper | PM_C0OUT | 89 | 58 | O | Default mapping: Comparator_E0 output |
PM_C1OUT | 90 | 59 | O | Default mapping: Comparator_E1 output | |
PM_DMAE0 | 88 | 57 | I | Default mapping: DMA external trigger input | |
PM_SMCLK | 88 | 57 | O | Default mapping: SMCLK clock output | |
PM_TA0.0 | 91 | 60 | I/O | Default mapping: TA0 CCR0 capture: CCI0A input, compare: Out0 | |
PM_TA0.1 | 20 | N/A | I/O | Default mapping: TA0 CCR1 capture: CCI1A input, compare: Out1 | |
PM_TA0.2 | 21 | N/A | I/O | Default mapping: TA0 CCR2 capture: CCI2A input, compare: Out2 | |
PM_TA0.3 | 22 | N/A | I/O | Default mapping: TA0 CCR3 capture: CCI3A input, compare: Out3 | |
PM_TA0.4 | 23 | N/A | I/O | Default mapping: TA0 CCR4 capture: CCI4A input, compare: Out4 | |
PM_TA0CLK | 89 | 58 | I | Default mapping: TA0 input clock | |
PM_TA1.2 | 28 | N/A | I/O | Default mapping: TA1 CCR2 capture: CCI2A input, compare: Out2 | |
PM_TA1.3 | 27 | N/A | I/O | Default mapping: TA1 CCR3 capture: CCI3A input, compare: Out3 | |
PM_TA1.4 | 26 | N/A | I/O | Default mapping: TA1 CCR4 capture: CCI4A input, compare: Out4 | |
PM_TA1CLK | 90 | 59 | I | Default mapping: TA1 input clock | |
PM_UCA1CLK | 17 | 14 | I/O | Default mapping: Clock signal input for eUSCI_A1 SPI slave mode
Clock signal output for eUSCI_A1 SPI master mode |
|
PM_UCA1RXD | 18 | 15 | I | Default mapping: Receive data for eUSCI_A1 UART mode | |
PM_UCA1SIMO | 19 | 16 | I/O | Default mapping: Slave in, master out for eUSCI_A1 SPI mode | |
PM_UCA1SOMI | 18 | 15 | I/O | Default mapping: Slave out, master in for eUSCI_A1 SPI mode | |
PM_UCA1STE | 16 | 13 | I/O | Default mapping: Slave transmit enable for eUSCI_A1 SPI mode | |
PM_UCA1TXD | 19 | 16 | O | Default mapping: Transmit data for eUSCI_A1 UART mode | |
PM_UCA2CLK | 33 | 20 | I/O | Default mapping: Clock signal input for eUSCI_A2 SPI slave mode
Clock signal output for eUSCI_A2 SPI master mode |
|
PM_UCA2RXD | 34 | 21 | I | Default mapping: Receive data for eUSCI_A2 UART mode | |
PM_UCA2SIMO | 35 | 22 | I/O | Default mapping: Slave in, master out for eUSCI_A2 SPI mode | |
PM_UCA2SOMI | 34 | 21 | I/O | Default mapping: Slave out, master in for eUSCI_A2 SPI mode | |
PM_UCA2STE | 32 | 19 | I/O | Default mapping: Slave transmit enable for eUSCI_A2 SPI mode | |
PM_UCA2TXD | 35 | 22 | O | Default mapping: Transmit data for eUSCI_A2 UART mode | |
Port Mapper (continued) | PM_UCB2CLK | 37 | 24 | I/O | Default mapping: Clock signal input for eUSCI_B2 SPI slave mode
Clock signal output for eUSCI_B2 SPI master mode |
PM_UCB2SCL | 39 | 26 | I | Default mapping: I2C clock for eUSCI_B2 I2C mode | |
PM_UCB2SDA | 38 | 25 | I/O | Default mapping: I2C data for eUSCI_B2 I2C mode | |
PM_UCB2SIMO | 38 | 25 | I/O | Default mapping: Slave in, master out for eUSCI_B2 SPI mode | |
PM_UCB2SOMI | 39 | 26 | I/O | Default mapping: Slave out, master in for eUSCI_B2 SPI mode | |
PM_UCB2STE | 36 | 23 | I/O | Default mapping: Slave transmit enable for eUSCI_B2 SPI mode | |
Power | AVCC1 | 45 | 32 | – | Analog power supply |
AVCC2 | 87 | 56 | – | Analog power supply | |
AVSS1 | 43 | 30 | – | Analog ground supply | |
AVSS2 | 84 | 53 | – | Analog ground supply | |
AVSS3 | 40 | 27 | – | Analog ground supply | |
DVCC1 | 13 | 10 | – | Digital power supply | |
DVCC2 | 73 | 48 | – | Digital power supply | |
DVSS1 | 15 | 12 | – | Digital ground supply | |
DVSS2 | 72 | 47 | – | Digital ground supply | |
DVSS3 | 82 | 51 | – | Must be connected to ground | |
VCORE(3) | 12 | 9 | – | Regulated core power supply (internal use only, no external current loading) | |
VSW | 14 | 11 | – | DC/DC converter switching output | |
RTC | RTCCLK | 59 | 34 | O | RTC_C clock calibration output |
Reference | VREF+ | 70 | 45 | O | Internal shared reference voltage positive terminal |
VREF- | 71 | 46 | O | Internal shared reference voltage negative terminal | |
VeREF+ | 70 | 45 | I | Positive terminal of external reference voltage to ADC | |
VeREF- | 71 | 46 | I | Negative terminal of external reference voltage to ADC (recommended to connect to onboard ground) | |
SPI | UCA0CLK | 5 | 2 | I/O | Clock signal input for eUSCI_A0 SPI slave mode
Clock signal output for eUSCI_A0 SPI master mode |
UCA0SIMO | 7 | 4 | I/O | Slave in, master out for eUSCI_A0 SPI mode | |
UCA0SOMI | 6 | 3 | I/O | Slave out, master in for eUSCI_A0 SPI mode | |
UCA0STE | 4 | 1 | I/O | Slave transmit enable for eUSCI_A0 SPI mode | |
UCA3CLK | 97 | N/A | I/O | Clock signal input for eUSCI_A3 SPI slave mode
Clock signal output for eUSCI_A3 SPI master mode |
|
UCA3SIMO | 99 | N/A | I/O | Slave in, master out for eUSCI_A3 SPI mode | |
UCA3SOMI | 98 | N/A | I/O | Slave out, master in for eUSCI_A3 SPI mode | |
UCA3STE | 96 | N/A | I/O | Slave transmit enable for eUSCI_A3 SPI mode | |
UCB0CLK | 9 | 6 | I/O | Clock signal input for eUSCI_B0 SPI slave mode
Clock signal output for eUSCI_B0 SPI master mode |
|
UCB0SIMO | 10 | 7 | I/O | Slave in, master out for eUSCI_B0 SPI mode | |
UCB0SOMI | 11 | 8 | I/O | Slave out, master in for eUSCI_B0 SPI mode | |
UCB0STE | 8 | 5 | I/O | Slave transmit enable for eUSCI_B0 SPI mode | |
UCB1CLK | 77 | N/A | I/O | Clock signal input for eUSCI_B1 SPI slave mode
Clock signal output for eUSCI_B1 SPI master mode |
|
UCB1SIMO | 78 | N/A | I/O | Slave in, master out for eUSCI_B1 SPI mode | |
UCB1SOMI | 79 | N/A | I/O | Slave out, master in for eUSCI_B1 SPI mode | |
UCB1STE | 76 | N/A | I/O | Slave transmit enable for eUSCI_B1 SPI mode | |
UCB3CLK | 1
31 |
18 | I/O | Clock signal input for eUSCI_B3 SPI slave mode
Clock signal output for eUSCI_B3 SPI master mode |
|
UCB3SIMO | 2
80 |
49 | I/O | Slave in, master out for eUSCI_B3 SPI mode | |
UCB3SOMI | 3
81 |
50 | I/O | Slave out, master in for eUSCI_B3 SPI mode | |
UCB3STE | 30
100 |
17 | I/O | Slave transmit enable for eUSCI_B3 SPI mode | |
System | NMI | 83 | 52 | I | External nonmaskable interrupt |
RSTn | 83 | 52 | I | External reset (active low) | |
SVMHOUT | 60 | 35 | O | SVMH output | |
Thermal | QFN Pad | N/A | Pad | – | QFN package exposed thermal pad. TI recommends connection to VSS. |
Timer | PM_TA1.1 | 29 | N/A | I/O | Default mapping: TA1 CCR1 capture: CCI1A input, compare: Out1 |
TA1.0 | 30 | 17 | I/O | TA1 CCR0 capture: CCI0A input, compare: Out0 | |
TA2.0 | 31 | 18 | I/O | TA2 CCR0 capture: CCI0A input, compare: Out0 | |
TA2.1 | 70 | 45 | I/O | TA2 CCR1 capture: CCI1A input, compare: Out1 | |
TA2.2 | 71 | 46 | I/O | TA2 CCR2 capture: CCI2A input, compare: Out2 | |
TA2.3 | 80 | 49 | I/O | TA2 CCR3 capture: CCI3A input, compare: Out3 | |
TA2.4 | 81 | 50 | I/O | TA2 CCR4 capture: CCI4A input, compare: Out4 | |
TA2CLK | 58 | 33 | I | TA2 input clock | |
TA3.0 | 24 | N/A | I/O | TA3 CCR0 capture: CCI0A input, compare: Out0 | |
TA3.1 | 25 | N/A | I/O | TA3 CCR1 capture: CCI1A input, compare: Out1 | |
TA3.2 | 46 | N/A | I/O | TA3 CCR2 capture: CCI2A input, compare: Out2 | |
TA3.3 | 74 | N/A | I/O | TA3 CCR3 capture: CCI3A input, compare: Out3 | |
TA3.4 | 75 | N/A | I/O | TA3 CCR4 capture: CCI4A input, compare: Out4 | |
TA3CLK | 47 | N/A | I | TA3 input clock | |
UART | UCA0RXD | 6 | 3 | I | Receive data for eUSCI_A0 UART mode |
UCA0TXD | 7 | 4 | O | Transmit data for eUSCI_A0 UART mode | |
UCA3RXD | 98 | N/A | I | Receive data for eUSCI_A3 UART mode | |
UCA3TXD | 99 | N/A | O | Transmit data for eUSCI_A3 UART mode |