Figure 4-2 shows the pinout of the 64-pin RGC package.
A. The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default mapping. See Section 6.9.2 for details.
B. A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
C. TI recommends connecting the thermal pad on the QFN package to DVSS.