ZHCSHI9B December 2017 – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
tSTE,LEAD | STE lead time, STE active to clock | 1.62 V | 45 | ns | ||
3.7 V | 20 | |||||
tSTE,LAG | STE lag time, Last clock to STE inactive | 1.62 V | 1 | ns | ||
3.7 V | 1 | |||||
tSTE,ACC | STE access time, STE active to SOMI data out | 1.62 V | 25 | ns | ||
3.7 V | 15 | |||||
tSTE,DIS | STE disable time, STE inactive to SOMI high impedance | 1.62 V | 18 | ns | ||
3.7 V | 14 | |||||
tSU,SI | SIMO input data setup time | 1.62 V | 3 | ns | ||
3.7 V | 2 | |||||
tHD,SI | SIMO input data hold time | 1.62 V | 0 | ns | ||
3.7 V | 0 | |||||
tVALID,SO | SOMI output data valid time(2) | UCLK edge to SOMI valid,
CL = 20 pF |
1.62 V | 35 | ns | |
3.7 V | 18 | |||||
tHD,SO | SOMI output data hold time(3) | CL = 20 pF | 1.62 V | 10 | ns | |
3.7 V | 6 |
Table 5-44 lists the supported clock frequencies of the eUSCI in I2C mode.