-
1器件概述
- 1.1
特性
- 1.2
应用
- 1.3
说明
- 1.4
功能框图
-
2修订历史记录
-
3Device Comparison
- 3.1
Related Products
-
4Terminal Configuration and Functions
- 4.1
Pin Diagrams
- 4.2
Pin Attributes
- 4.3
Signal Descriptions
- Table 4-2
Signal Descriptions
- 4.4
Pin Multiplexing
- 4.5
Buffer Types
- 4.6
Connection of Unused Pins
-
5Specifications
- 5.1
Absolute Maximum Ratings
- 5.2
ESD Ratings
- 5.3
Recommended Operating Conditions
- 5.4
Active Mode Supply Current Into VCC Excluding External Current
- 5.5
Typical Characteristics, Active Mode Supply Currents
- 5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
- 5.7
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
- 5.8
Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
- 5.9
Typical Characteristics, Low-Power Mode Supply Currents
- 5.10
Typical Characteristics, Current Consumption per Module
- 5.11
Thermal Packaging Characteristics
- 5.12
Timing and Switching Characteristics
- 5.12.1
Power Supply Sequencing
- Table 5-1
Brownout and Device Reset Power Ramp Requirements
- Table 5-2
SVS
- 5.12.2
Reset Timing
- Table 5-3
Reset Input
- 5.12.3
Clock Specifications
- Table 5-4
Low-Frequency Crystal Oscillator, LFXT
- Table 5-5
High-Frequency Crystal Oscillator, HFXT
- Table 5-6
DCO
- Table 5-7
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- Table 5-8
Module Oscillator (MODOSC)
- 5.12.4
Wake-up Characteristics
- Table 5-9
Wake-up Times From Low-Power Modes and Reset
- 5.12.4.1
Typical Characteristics, Average LPM Currents vs Wake-up Frequency
- Table 5-10
Typical Wake-up Charge
- 5.12.5
Digital I/Os
- Table 5-11
Digital Inputs
- Table 5-12
Digital Outputs
- 5.12.5.1
Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
- Table 5-13
Pin-Oscillator Frequency, Ports Px
- 5.12.5.2
Typical Characteristics, Pin-Oscillator Frequency
- 5.12.6
LEA (Low-Energy Accelerator) (MSP430FR599x Only)
- Table 5-14
Low Energy Accelerator Performance
- 5.12.7
Timer_A and Timer_B
- Table 5-15
Timer_A
- Table 5-16
Timer_B
- 5.12.8
eUSCI
- Table 5-17
eUSCI (UART Mode) Clock Frequency
- Table 5-18
eUSCI (UART Mode)
- Table 5-19
eUSCI (SPI Master Mode) Clock Frequency
- Table 5-20
eUSCI (SPI Master Mode)
- Table 5-21
eUSCI (SPI Slave Mode)
- Table 5-22
eUSCI (I2C Mode)
- 5.12.9
ADC12_B
- Table 5-23
12-Bit ADC, Power Supply and Input Range Conditions
- Table 5-24
12-Bit ADC, Timing Parameters
- Table 5-25
12-Bit ADC, Linearity Parameters
- Table 5-26
12-Bit ADC, Dynamic Performance With External Reference
- Table 5-27
12-Bit ADC, Dynamic Performance With Internal Reference
- Table 5-28
12-Bit ADC, Temperature Sensor and Built-In V1/2
- Table 5-29
12-Bit ADC, External Reference
- 5.12.10
Reference
- Table 5-30
REF, Built-In Reference
- 5.12.11
Comparator
- Table 5-31
Comparator_E
- 5.12.12
FRAM
- Table 5-32
FRAM
- 5.12.13
Emulation and Debug
- Table 5-33
JTAG and Spy-Bi-Wire Interface
-
6Detailed Description
- 6.1
Overview
- 6.2
CPU
- 6.3
Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
- 6.4
Operating Modes
- 6.4.1
Peripherals in Low-Power Modes
- 6.4.2
Idle Currents of Peripherals in LPM3 and LPM4
- 6.5
Interrupt Vector Table and Signatures
- 6.6
Bootloader (BSL)
- 6.7
JTAG Operation
- 6.7.1
JTAG Standard Interface
- 6.7.2
Spy-Bi-Wire Interface
- 6.8
FRAM Controller A (FRCTL_A)
- 6.9
RAM
- 6.10
Tiny RAM
- 6.11
Memory Protection Unit (MPU) Including IP Encapsulation
- 6.12
Peripherals
- 6.12.1
Digital I/O
- 6.12.2
Oscillator and Clock System (CS)
- 6.12.3
Power-Management Module (PMM)
- 6.12.4
Hardware Multiplier (MPY)
- 6.12.5
Real-Time Clock (RTC_C)
- 6.12.6
Watchdog Timer (WDT_A)
- 6.12.7
System Module (SYS)
- 6.12.8
DMA Controller
- 6.12.9
Enhanced Universal Serial Communication Interface (eUSCI)
- 6.12.10
TA0, TA1, and TA4
- 6.12.11
TA2 and TA3
- 6.12.12
TB0
- 6.12.13
ADC12_B
- 6.12.14
Comparator_E
- 6.12.15
CRC16
- 6.12.16
CRC32
- 6.12.17
AES256 Accelerator
- 6.12.18
True Random Seed
- 6.12.19
Shared Reference (REF)
- 6.12.20
Embedded Emulation
- 6.12.20.1
Embedded Emulation Module (EEM) (S Version)
- 6.12.20.2
EnergyTrace++ Technology
- 6.13
Input/Output Diagrams
- 6.13.1
Capacitive Touch Functionality on Ports P1 to P8, and PJ
- 6.13.2
Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
- 6.13.3
Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
- 6.13.4
Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
- 6.13.5
Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
- 6.13.6
Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
- 6.13.7
Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
- 6.13.8
Port P2 (P2.7) Input/Output With Schmitt Trigger
- 6.13.9
Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
- 6.13.10
Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
- 6.13.11
Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
- 6.13.12
Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
- 6.13.13
Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
- 6.13.14
Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
- 6.13.15
Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
- 6.13.16
Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
- 6.13.17
Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
- 6.13.18
Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
- 6.13.19
Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
- 6.13.20
Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
- 6.14
Device Descriptors (TLV)
- 6.15
Memory Map
- 6.15.1
Peripheral File Map
- 6.16
Identification
- 6.16.1
Revision Identification
- 6.16.2
Device Identification
- 6.16.3
JTAG Identification
-
7Applications, Implementation, and Layout
- 7.1
Device Connection and Layout Fundamentals
- 7.1.1
Power Supply Decoupling and Bulk Capacitors
- 7.1.2
External Oscillator
- 7.1.3
JTAG
- 7.1.4
Reset
- 7.1.5
Unused Pins
- 7.1.6
General Layout Recommendations
- 7.1.7
Do's and Don'ts
- 7.2
Peripheral- and Interface-Specific Design Information
- 7.2.1
ADC12_B Peripheral
- 7.2.1.1
Partial Schematic
- 7.2.1.2
Design Requirements
- 7.2.1.3
Detailed Design Procedure
- 7.2.1.4
Layout Guidelines
-
8器件和文档支持
- 8.1
入门和下一步
- 8.2
器件命名规则
- 8.3
工具与软件
- 8.4
文档支持
- 8.5
相关链接
- 8.6
社区资源
- 8.7
商标
- 8.8
静电放电警告
- 8.9
出口管制提示
- 8.10
术语表
-
9机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
-
PM|64
-
ZVW|87
-
PN|80
-
RGZ|48
散热焊盘机械数据 (封装 | 引脚)
订购信息