ZHCSCN8A May 2014 – September 2018 MSP430F6745A , MSP430F6746A , MSP430F6747A , MSP430F6748A , MSP430F6749A , MSP430F6765A , MSP430F6766A , MSP430F6767A , MSP430F6768A , MSP430F6769A , MSP430F6775A , MSP430F6776A , MSP430F6777A , MSP430F6778A , MSP430F6779A
PRODUCTION DATA.
The port mapping controller allows flexible and reconfigurable mapping of digital functions to ports P2, P3, and P4 (see Table 6-11). Table 6-12 lists the default settings for all pins that support port mapping.
VALUE | PxMAPy MNEMONIC | INPUT PIN FUNCTION | OUTPUT PIN FUNCTION |
---|---|---|---|
0 | PM_NONE | None | DVSS |
1 | PM_UCA0RXD | eUSCI_A0 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA0SOMI | eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) | ||
2 | PM_UCA0TXD | eUSCI_A0 UART TXD (direction controlled by eUSCI – Output) | |
PM_UCA0SIMO | eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) | ||
3 | PM_UCA0CLK | eUSCI_A0 clock input/output (direction controlled by eUSCI) | |
4 | PM_UCA0STE | eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI) | |
5 | PM_UCA1RXD | eUSCI_A1 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA1SOMI | eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) | ||
6 | PM_UCA1TXD | eUSCI_A1 UART TXD (direction controlled by eUSCI – Output) | |
PM_UCA1SIMO | eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) | ||
7 | PM_UCA1CLK | eUSCI_A1 clock input/output (direction controlled by eUSCI) | |
8 | PM_UCA1STE | eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI) | |
9 | PM_UCA2RXD | eUSCI_A2 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA2SOMI | eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) | ||
10 | PM_UCA2TXD | eUSCI_A2 UART TXD (direction controlled by eUSCI – Output) | |
PM_ UCA2SIMO | eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) | ||
11 | PM_UCA2CLK | eUSCI_A2 clock input/output (direction controlled by eUSCI) | |
12 | PM_UCA2STE | eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI) | |
13 | PM_UCA3RXD | eUSCI_A3 UART RXD (direction controlled by eUSCI – Input) | |
PM_UCA3SOMI | eUSCI_A3 SPI slave out master in (direction controlled by eUSCI) | ||
14 | PM_UCA3TXD | eUSCI_A3 UART TXD (direction controlled by eUSCI – Output) | |
PM_ UCA3SIMO | eUSCI_A3 SPI slave in master out (direction controlled by eUSCI) | ||
15 | PM_UCA3CLK | eUSCI_A3 clock input/output (direction controlled by eUSCI) | |
16 | PM_UCA3STE | eUSCI_A3 SPI slave transmit enable (direction controlled by eUSCI) | |
17 | PM_UCB0SIMO | eUSCI_B0 SPI slave in master out (direction controlled by eUSCI) | |
PM_UCB0SDA | eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) | ||
18 | PM_UCB0SOMI | eUSCI_B0 SPI slave out master in (direction controlled by eUSCI) | |
PM_UCB0SCL | eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) | ||
19 | PM_UCB0CLK | eUSCI_B0 clock input/output (direction controlled by eUSCI) | |
20 | PM_UCB0STE | eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI) | |
21 | PM_UCB1SIMO | eUSCI_B1 SPI slave in master out (direction controlled by eUSCI) | |
PM_UCB1SDA | eUSCI_B1 I2C data (open drain and direction controlled by eUSCI) | ||
22 | PM_UCB1SOMI | eUSCI_B1 SPI slave out master in (direction controlled by eUSCI) | |
PM_UCB1SCL | eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI) | ||
23 | PM_UCB1CLK | eUSCI_B1 clock input/output (direction controlled by eUSCI) | |
24 | PM_UCB1STE | eUSCI_B1 SPI slave transmit enable (direction controlled by eUSCI) | |
25 | PM_TA0.0 | TA0 CCR0 capture input CCI0A | TA0 CCR0 compare output Out0 |
26 | PM_TA0.1 | TA0 CCR1 capture input CCI1A | TA0 CCR1 compare output Out1 |
27 | PM_TA0.2 | TA0 CCR2 capture input CCI2A | TA0 CCR2 compare output Out2 |
28 | PM_TA1.0 | TA1 CCR0 capture input CCI0A | TA1 CCR0 compare output Out0 |
29 | PM_TA2.0 | TA2 CCR0 capture input CCI0A | TA2 CCR0 compare output Out0 |
30 | PM_TA3.0 | TA3 CCR0 capture input CCI0A | TA3 CCR0 compare output Out0 |
31 (0FFh)(1) | PM_ANALOG | Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. |
PIN NAME | PxMAPy MNEMONIC | INPUT PIN FUNCTION | OUTPUT PIN FUNCTION | |
---|---|---|---|---|
PEU | PZ | |||
P2.0/PM_TA0.0 | P2.0/PM_TA0.0/COM4 | PM_TA0.0 | TA0 CCR0 capture input CCI0A | TA0 CCR0 compare output Out0 |
P2.1/PM_TA0.1 | P2.1/PM_TA0.1/COM5 | PM_TA0.1 | TA0 CCR1 capture input CCI1A | TA0 CCR1 compare output Out1 |
P2.2/PM_TA0.2 | P2.2/PM_TA0.2/COM6 | PM_TA0.2 | TA0 CCR2 capture input CCI2A | TA0 CCR2 compare output Out2 |
P2.3/PM_TA1.0 | P2.3/PM_TA1.0/COM7 | PM_TA1.0 | TA1 CCR0 capture input CCI0A | TA1 CCR0 compare output Out0 |
P2.4/PM_TA2.0 | P1.1/PM_TA2.0/R23 | PM_TA2.0 | TA2 CCR0 capture input CCI0A | TA2 CCR0 compare output Out0 |
P2.5/PM_UCB0SOMI/ PM_UCB0SCL | P2.0/PM_UCB0SOMI/ PM_UCB0SCL/R13 | PM_UCB0SOMI/ PM_UCB0SCL | eUSCI_B0 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI) |
|
P2.6/PM_UCB0SIMO/ PM_UCB0SDA | P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03 | PM_UCB0SIMO/ PM_UCB0SDA | eUSCI_B0 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI) |
|
P2.7/PM_UCB0CLK | P2.7/PM_UCB0CLK/CB2 | PM_UCB0CLK | eUSCI_B0 clock input/output (direction controlled by eUSCI) | |
P3.0/PM_UCA0RXD/ PM_UCA0SOMI | P3.0/PM_UCA0RXD/ PM_UCA0SOMI | PM_UCA0RXD/ PM_UCA0SOMI | eUSCI_A0 UART RXD (direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI) |
|
P3.1/PM_UCA0TXD/ PM_UCA0SIMO | P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39 | PM_UCA0TXD/ PM_UCA0SIMO | eUSCI_A0 UART TXD (direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI) |
|
P3.2/PM_UCA0CLK | P3.2/PM_UCA0CLK/S38 | PM_UCA0CLK | eUSCI_A0 clock input/output (direction controlled by eUSCI) | |
P3.3/PM_UCA1CLK | P3.3/PM_UCA1CLK/S37 | PM_UCA1CLK | eUSCI_A1 clock input/output (direction controlled by eUSCI) | |
P3.4/PM_UCA1RXD/ PM_UCA1SOMI/ | P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36 | PM_UCA1RXD/ PM_UCA1SOMI | eUSCI_A1 UART RXD (direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI) |
|
P3.5/PM_UCA1TXD/ PM_UCA1SIMO | P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 | PM_UCA1TXD/ PM_UCA1SIMO | eUSCI_A1 UART TXD (direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI) |
|
P3.6/PM_UCA2RXD/ PM_UCA2SOMI/ | P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34 | PM_UCA2RXD/ PM_UCA2SOMI | eUSCI_A2 UART RXD (direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI) |
|
P3.7/PM_UCA2TXD/ PM_UCA2SIMO | P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33 | PM_UCA2TXD/ PM_UCA2SIMO | eUSCI_A2 UART TXD (direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI) |
|
P4.0/PM_UCA2CLK | P4.0/PM_UCA2CLK/S32 | PM_UCA2CLK | eUSCI_A2 clock input/output (direction controlled by eUSCI) | |
P4.1/PM_UCA3RXD/ PM_UCA3SOMI/ | P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 | PM_UCA3RXD/ PM_UCA3SOMI | eUSCI_A3 UART RXD (direction controlled by eUSCI – input),
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI) |
|
P4.2/PM_UCA3TXD/ PM_UCA3SIMO | P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30 | PM_UCA3TXD/ PM_UCA3SIMO | eUSCI_A3 UART TXD (direction controlled by eUSCI – output),
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI) |
|
P4.3/PM_UCA3CLK | P4.3/PM_UCA3CLK/S29 | PM_UCA3CLK | eUSCI_A3 clock input/output (direction controlled by eUSCI) | |
P4.4/PM_UCB1SOMI/ PM_UCB1SCL | P4.4/PM_UCB1SOMI/ PM_UCB1SCL/S28 | PM_UCB1SOMI/ PM_UCB1SCL | eUSCI_B1 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI) |
|
P4.5/PM_UCB1SIMO/ PM_UCB1SDA | P4.5/PM_UCB1SIMO/ PM_UCB1SDA/S27 | PM_UCB1SIMO/ PM_UCB1SDA | eUSCI_B1 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI) |
|
P4.6/PM_UCB1CLK | P4.6/PM_UCB1CLK/S26 | PM_UCB1CLK | eUSCI_B1 clock input/output (direction controlled by eUSCI) | |
P4.7/PM_TA3.0 | P4.7/PM_TA3.0/S25 | PM_TA3.0 | TA3 CCR0 capture input CCI0A | TA3 CCR0 compare output Out0 |