ZHCS482F
July 2011 – September 2018
MSP430F5340
,
MSP430F5341
,
MSP430F5342
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
功能方框图
2
修订历史记录
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Signal Descriptions
Table 4-1
Signal Descriptions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
5.6
Thermal Resistance Characteristics, VQFN (RGZ) Package
5.7
Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
5.8
Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
5.9
Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
5.10
Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
5.11
Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
5.12
Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
5.13
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
5.14
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
5.15
Crystal Oscillator, XT1, Low-Frequency Mode
5.16
Crystal Oscillator, XT2
5.17
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
5.18
Internal Reference, Low-Frequency Oscillator (REFO)
5.19
DCO Frequency
5.20
PMM, Brownout Reset (BOR)
5.21
PMM, Core Voltage
5.22
PMM, SVS High Side
5.23
PMM, SVM High Side
5.24
PMM, SVS Low Side
5.25
PMM, SVM Low Side
5.26
Wake-up Times From Low-Power Modes and Reset
5.27
Timer_A
5.28
Timer_B
5.29
USCI (UART Mode) Clock Frequency
5.30
USCI (UART Mode)
5.31
USCI (SPI Master Mode) Clock Frequency
5.32
USCI (SPI Master Mode)
5.33
USCI (SPI Slave Mode)
5.34
USCI (I2C Mode)
5.35
12-Bit ADC, Power Supply and Input Range Conditions
5.36
12-Bit ADC, Timing Parameters
5.37
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
5.38
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
5.39
12-Bit ADC, Temperature Sensor and Built-In VMID
5.40
REF, External Reference
5.41
REF, Built-In Reference
5.42
Comparator_B
5.43
Flash Memory
5.44
JTAG and Spy-Bi-Wire Interface
6
Detailed Description
6.1
CPU
6.2
Operating Modes
6.3
Interrupt Vector Addresses
6.4
Memory Organization
6.5
Bootloader (BSL)
6.6
JTAG Operation
6.6.1
JTAG Standard Interface
6.6.2
Spy-Bi-Wire Interface
6.7
Flash Memory
6.8
RAM
6.9
Peripherals
6.9.1
Digital I/O
6.9.2
Port Mapping Controller
6.9.3
Oscillator and System Clock
6.9.4
Power Management Module (PMM)
6.9.5
Hardware Multiplier
6.9.6
Real-Time Clock (RTC_A)
6.9.7
Watchdog Timer (WDT_A)
6.9.8
System Module (SYS)
6.9.9
DMA Controller
6.9.10
Universal Serial Communication Interface (USCI)
6.9.11
TA0
6.9.12
TA1
6.9.13
TA2
6.9.14
TB0
6.9.15
Comparator_B
6.9.16
ADC12_A
6.9.17
CRC16
6.9.18
Reference (REF) Module Voltage Reference
6.9.19
Embedded Emulation Module (EEM)
6.9.20
Peripheral File Map
6.10
Input/Output Diagrams
6.10.1
Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
6.10.2
Port P2 (P2.7) Input/Output With Schmitt Trigger
6.10.3
Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
6.10.4
Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
6.10.5
Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
6.10.6
Port P5 (P5.2) Input/Output With Schmitt Trigger
6.10.7
Port P5 (P5.3) Input/Output With Schmitt Trigger
6.10.8
Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
6.10.9
Port P5 (P5.7) Input/Output With Schmitt Trigger
6.10.10
Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
6.10.11
Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
6.10.12
Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
6.11
Device Descriptors
7
器件和文档支持
7.1
开始使用
7.2
Device Nomenclature
7.3
工具与软件
7.4
文档支持
7.5
相关链接
7.6
社区资源
7.7
商标
7.8
静电放电警告
7.9
Export Control Notice
7.10
Glossary
8
机械,封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RGZ|48
MPQF123F
散热焊盘机械数据 (封装 | 引脚)
RGZ|48
QFND031W
订购信息
zhcs482f_oa
zhcs482f_pm
1.1
特性
低电源电压范围:
3.6V 到低至 1.8V
超低功耗
激活模式 (AM):所有系统时钟激活
8MHz 时为 290µA/MHz、3V、闪存程序执行(典型值)
8MHz 时为 150µA/MHz、3V、RAM 程序执行(典型值)
待机模式 (LPM3):
带有晶振的实时时钟 (RTC)、看门狗、电源监控器可用、完全 RAM 保持、快速唤醒:
2.2V 时为 1.9µA,3V 时为 2.1µA(典型值)
低功耗振荡器 (VLO)、通用计数器、看门狗和电源监控器可用、完全 RAM 保持,快速唤醒:
3V 时为 1.4µA(典型值)
关闭模式 (LPM4):
完全 RAM 保持、电源监控器可用、快速唤醒:
3V 时为 1.1µA(典型值)
关断模式 (LPM4.5):
3V 时为 0.18µA(典型值)
在 3.5µs(典型值)内从待机模式唤醒
16 位 RISC 架构,扩展存储器,
高达 25MHz 的系统时钟
灵活的电源管理系统
内置可编程的低压降稳压器 (LDO)
电源电压监控、监视、和临时限电
统一时钟系统
针对频率稳定的锁相环 (FLL) 控制环路
低功耗低频内部时钟源 (VLO)
低频修整内部基准源 (REFO)
32kHz 手表晶振 (XT1)
高达 32MHz 的高频晶振 (XT2)
具有 5 个捕捉/比较寄存器的 16 位计时器 TA0,Timer_A
具有 3 个捕捉/比较寄存器的 16 位计时器 TA1,Timer_A
具有 3 个捕捉/比较寄存器的 16 位计时器 TA2,Timer_A
具有 7 个捕捉/比较影子寄存器的 16 位计时器 TB0,Timer_B
两个通用串行通信接口 (USCI)
USCI_A0 和 USCI_A1 均支持:
具有自动波特率检测功能的增强型通用异步收发器 (UART)
IrDA 编码和解码
同步串行外设接口 (SPI)
USCI_B0 和 USCI_B1 每个都支持:
I
2
C
同步串行外设接口 (SPI)
具有内部基准、采样保持、和自动扫描功能的 12 位模数转换器 (ADC)
比较器
硬件乘法器支持 32 位运算
串行板上编程,无需外部编程电压
3 通道内部 DMA
具有 RTC 特性的基本计时器
器件比较
汇总了可用的产品系列成员