ZHCSIH0B December 2017 – July 2019 LP87702-Q1
In this mode the PGx signal shows the validity of the requested voltages continuously. Mode is selected by setting PGx_MODE bit to 1 in PG_CTRL register.
For the continuous mode of operation, PGx behaves as follows:
When invalid output voltage of monitored converter is detected, corresponding bit in PG0_FAULT or PG1_FAULT register is set to 1 and PGx signal becomes inactive. The PG0_FAULT and PG1_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing 1 to the bit. The PGx signal indicates also interrupts from VANA, VMON1 and VMON2 inputs and thermal warning and shutdown. All are cleared by clearing the interrupt bits.
When converter voltage is transitioning from one target voltage to another, the PGx signal is set inactive.
When PGx signal becomes inactive, the source for the fault can be read from PGx_FAULT register. If the invalid output voltage becomes valid again the PGx signal becomes active. Thus the PGx signal shows all the time if the monitored output voltages are valid. An example of PGx pin operation in continuous mode is shown in Figure 17.
The PGx signal can be also configured so that it maintains inactive state even when the monitored outputs are valid but there are PG_FAULT_x bits pending clearance. This type of operation is selected by setting PGOOD_FAULT_GATES_PGx bit to 1.