ZHCSIH0A December   2017  – July 2018 LP87702-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     降压效率与输出电流的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Step-Down DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
      2. 7.3.2  Boost Converter
      3. 7.3.3  Spread-Spectrum Mode
      4. 7.3.4  Sync Clock Functionality
      5. 7.3.5  Power-Up
      6. 7.3.6  Buck and Boost Control
        1. 7.3.6.1 Enabling and Disabling Converters
        2. 7.3.6.2 Changing Buck Output Voltage
      7. 7.3.7  Enable and Disable Sequences
      8. 7.3.8  Window Watchdog
      9. 7.3.9  Device Reset Scenarios
      10. 7.3.10 Diagnostics and Protection Features
        1. 7.3.10.1 Voltage Monitorings
        2. 7.3.10.2 Interrupts
        3. 7.3.10.3 Power-Good Information to Interrupt and PG0 and PG1 Pins
          1. 7.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 7.3.10.3.2 PGx pin Operation in Continuous Mode
          3. 7.3.10.3.3 Summary of PG0, PG1 Gated and Continuous Operating Modes
        4. 7.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 7.3.10.4.1 Output Power Limit
          2. 7.3.10.4.2 Thermal Warning
        5. 7.3.10.5 Protections Causing Converter Disable
          1. 7.3.10.5.1 Short-Circuit and Overload Protection
          2. 7.3.10.5.2 Overvoltage Protection
          3. 7.3.10.5.3 Thermal Shutdown
        6. 7.3.10.6 Protections Causing Device Power Down
          1. 7.3.10.6.1 Undervoltage Lockout
      11. 7.3.11 OTP Error Correction
      12. 7.3.12 Operation of GPO Signals
      13. 7.3.13 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 LP8770_map Registers
          1. 7.6.1.1.1  DEV_REV Register (Offset = 0h) [reset = 0h]
            1. Table 11. DEV_REV Register Field Descriptions
          2. 7.6.1.1.2  OTP_CODE Register (Offset = 1h) [reset = 0h]
            1. Table 12. OTP_CODE Register Field Descriptions
          3. 7.6.1.1.3  BUCK0_CTRL_1 Register (Offset = 2h) [reset = 8h]
            1. Table 13. BUCK0_CTRL_1 Register Field Descriptions
          4. 7.6.1.1.4  BUCK0_CTRL_2 Register (Offset = 3h) [reset = 1Ah]
            1. Table 14. BUCK0_CTRL_2 Register Field Descriptions
          5. 7.6.1.1.5  BUCK1_CTRL_1 Register (Offset = 4h) [reset = 8h]
            1. Table 15. BUCK1_CTRL_1 Register Field Descriptions
          6. 7.6.1.1.6  BUCK1_CTRL_2 Register (Offset = 5h) [reset = 1Ah]
            1. Table 16. BUCK1_CTRL_2 Register Field Descriptions
          7. 7.6.1.1.7  BUCK0_VOUT Register (Offset = 6h) [reset = 0h]
            1. Table 17. BUCK0_VOUT Register Field Descriptions
          8. 7.6.1.1.8  BUCK1_VOUT Register (Offset = 7h) [reset = 0h]
            1. Table 18. BUCK1_VOUT Register Field Descriptions
          9. 7.6.1.1.9  BOOST_CTRL Register (Offset = 8h) [reset = 8h]
            1. Table 19. BOOST_CTRL Register Field Descriptions
          10. 7.6.1.1.10 BUCK0_DELAY Register (Offset = 9h) [reset = 0h]
            1. Table 20. BUCK0_DELAY Register Field Descriptions
          11. 7.6.1.1.11 BUCK1_DELAY Register (Offset = Ah) [reset = 0h]
            1. Table 21. BUCK1_DELAY Register Field Descriptions
          12. 7.6.1.1.12 BOOST_DELAY Register (Offset = Bh) [reset = 0h]
            1. Table 22. BOOST_DELAY Register Field Descriptions
          13. 7.6.1.1.13 GPO0_DELAY Register (Offset = Ch) [reset = 0h]
            1. Table 23. GPO0_DELAY Register Field Descriptions
          14. 7.6.1.1.14 GPO1_DELAY Register (Offset = Dh) [reset = 0h]
            1. Table 24. GPO1_DELAY Register Field Descriptions
          15. 7.6.1.1.15 GPO2_DELAY Register (Offset = Eh) [reset = 0h]
            1. Table 25. GPO2_DELAY Register Field Descriptions
          16. 7.6.1.1.16 GPO_CONTROL_1 Register (Offset = Fh) [reset = AAh]
            1. Table 26. GPO_CONTROL_1 Register Field Descriptions
          17. 7.6.1.1.17 GPO_CONTROL_2 Register (Offset = 10h) [reset = Ah]
            1. Table 27. GPO_CONTROL_2 Register Field Descriptions
          18. 7.6.1.1.18 CONFIG Register (Offset = 11h) [reset = 3Ch]
            1. Table 28. CONFIG Register Field Descriptions
          19. 7.6.1.1.19 PLL_CTRL Register (Offset = 12h) [reset = 2h]
            1. Table 29. PLL_CTRL Register Field Descriptions
          20. 7.6.1.1.20 PGOOD_CTRL Register (Offset = 13h) [reset = 0h]
            1. Table 30. PGOOD_CTRL Register Field Descriptions
          21. 7.6.1.1.21 PGOOD_LEVEL_1 Register (Offset = 14h) [reset = 0h]
            1. Table 31. PGOOD_LEVEL_1 Register Field Descriptions
          22. 7.6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h) [reset = 0h]
            1. Table 32. PGOOD_LEVEL_2 Register Field Descriptions
          23. 7.6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h) [reset = 0h]
            1. Table 33. PGOOD_LEVEL_3 Register Field Descriptions
          24. 7.6.1.1.24 PG_CTRL Register (Offset = 17h) [reset = 2h]
            1. Table 34. PG_CTRL Register Field Descriptions
          25. 7.6.1.1.25 PG0_CTRL Register (Offset = 18h) [reset = 0h]
            1. Table 35. PG0_CTRL Register Field Descriptions
          26. 7.6.1.1.26 PG0_FAULT Register (Offset = 19h) [reset = 0h]
            1. Table 36. PG0_FAULT Register Field Descriptions
          27. 7.6.1.1.27 PG1_CTRL Register (Offset = 1Ah) [reset = 0h]
            1. Table 37. PG1_CTRL Register Field Descriptions
          28. 7.6.1.1.28 PG1_FAULT Register (Offset = 1Bh) [reset = 0h]
            1. Table 38. PG1_FAULT Register Field Descriptions
          29. 7.6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch) [reset = 0h]
            1. Table 39. WD_CTRL_1 Register Field Descriptions
          30. 7.6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh) [reset = 1h]
            1. Table 40. WD_CTRL_2 Register Field Descriptions
          31. 7.6.1.1.31 WD_STATUS Register (Offset = 1Eh) [reset = 0h]
            1. Table 41. WD_STATUS Register Field Descriptions
          32. 7.6.1.1.32 RESET Register (Offset = 1Fh) [reset = 0h]
            1. Table 42. RESET Register Field Descriptions
          33. 7.6.1.1.33 INT_TOP_1 Register (Offset = 20h) [reset = 0h]
            1. Table 43. INT_TOP_1 Register Field Descriptions
          34. 7.6.1.1.34 INT_TOP_2 Register (Offset = 21h) [reset = 0h]
            1. Table 44. INT_TOP_2 Register Field Descriptions
          35. 7.6.1.1.35 INT_BUCK Register (Offset = 22h) [reset = 0h]
            1. Table 45. INT_BUCK Register Field Descriptions
          36. 7.6.1.1.36 INT_BOOST Register (Offset = 23h) [reset = 0h]
            1. Table 46. INT_BOOST Register Field Descriptions
          37. 7.6.1.1.37 INT_DIAG Register (Offset = 24h) [reset = 0h]
            1. Table 47. INT_DIAG Register Field Descriptions
          38. 7.6.1.1.38 TOP_STATUS Register (Offset = 25h) [reset = 0h]
            1. Table 48. TOP_STATUS Register Field Descriptions
          39. 7.6.1.1.39 BUCK_STATUS Register (Offset = 26h) [reset = 0h]
            1. Table 49. BUCK_STATUS Register Field Descriptions
          40. 7.6.1.1.40 BOOST_STATUS Register (Offset = 27h) [reset = 0h]
            1. Table 50. BOOST_STATUS Register Field Descriptions
          41. 7.6.1.1.41 DIAG_STATUS Register (Offset = 28h) [reset = 0h]
            1. Table 51. DIAG_STATUS Register Field Descriptions
          42. 7.6.1.1.42 TOP_MASK_1 Register (Offset = 29h) [reset = 0h]
            1. Table 52. TOP_MASK_1 Register Field Descriptions
          43. 7.6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah) [reset = 1h]
            1. Table 53. TOP_MASK_2 Register Field Descriptions
          44. 7.6.1.1.44 BUCK_MASK Register (Offset = 2Bh) [reset = 0h]
            1. Table 54. BUCK_MASK Register Field Descriptions
          45. 7.6.1.1.45 BOOST_MASK Register (Offset = 2Ch) [reset = 0h]
            1. Table 55. BOOST_MASK Register Field Descriptions
          46. 7.6.1.1.46 DIAG_MASK Register (Offset = 2Dh) [reset = 0h]
            1. Table 56. DIAG_MASK Register Field Descriptions
          47. 7.6.1.1.47 SEL_I_LOAD Register (Offset = 2Eh) [reset = 0h]
            1. Table 57. SEL_I_LOAD Register Field Descriptions
          48. 7.6.1.1.48 I_LOAD_2 Register (Offset = 2Fh) [reset = 0h]
            1. Table 58. I_LOAD_2 Register Field Descriptions
          49. 7.6.1.1.49 I_LOAD_1 Register (Offset = 30h) [reset = 0h]
            1. Table 59. I_LOAD_1 Register Field Descriptions
          50. 7.6.1.1.50 FREQ_SEL Register (Offset = 31h) [reset = 0h]
            1. Table 60. FREQ_SEL Register Field Descriptions
          51. 7.6.1.1.51 BOOST_ILIM_CTRL Register (Offset = 32h) [reset = 0h]
            1. Table 61. BOOST_ILIM_CTRL Register Field Descriptions
          52. 7.6.1.1.52 ECC_STATUS Register (Offset = 33h) [reset = 0h]
            1. Table 62. ECC_STATUS Register Field Descriptions
          53. 7.6.1.1.53 WD_DIS_CTRL_CODE Register (Offset = 34h) [reset = 0h]
            1. Table 63. WD_DIS_CTRL_CODE Register Field Descriptions
          54. 7.6.1.1.54 WD_DIS_CONTROL Register (Offset = 35h) [reset = 0h]
            1. Table 64. WD_DIS_CONTROL Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Buck Input Capacitor Selection
          3. 8.2.2.1.3 Buck Output Capacitor Selection
          4. 8.2.2.1.4 Boost Input Capacitor Selection
          5. 8.2.2.1.5 Boost Output Capacitor Selection
          6. 8.2.2.1.6 Supply Filtering Components
      3. 8.2.3 Current Limit vs Maximum Output Current
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx = 1 V, unless otherwise noted. (1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN_BUCK Input filtering capacitance for buck converters Effective capacitance, connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT_BUCK Output filtering capacitance for buck converters Effective total capacitance. Maximum includes POL capacitance 15 22 100 µF
COUT_BUCK_POL Point-of-load (POL) capacitance for buck converters Optional POL capacitance 22 µF
COUT_BST Output filtering capacitance for boost converter Effective capacitance 10 22 40 µF
ESRC Input and output capacitor ESR [1-10] MHz 2 10
LBUCK Inductor for buck converters Inductance of the inductor 0.47 µH
–30% 30%
LBST Inductor for boost converters Inductance of the inductor, 2-MHz switching 1 µH
Inductance of the inductor, 4-MHz switching 1
Inductance of the inductor –30% 30%
DCRL Inductor DCR 25
BUCK CONVERTERS
V(VIN_Bx), V(VANA) Input voltage range 2.8 3.3 5.5 V
VOUT_Bx Output voltage Programmable voltage range 0.7 1 3.36 V
Step size, 0.7 V ≤ VOUT < 0.73 V 10 mV
Step size, 0.73 V ≤ VOUT < 1.4 V 5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20
IOUT_Bx Output current Output current 3.5 (3) A
Minimum voltage difference between V(VIN_Bx) and VOUT_Bx for electrical characteristics V(VIN_Bx) – VOUT, IOUT_Bx  ≤ 2 A 0.8 V
V(VIN_Bx) – VOUT, IOUT_Bx  > 2 A 1
DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Force PWM mode, VOUT ˂ 1.0 V –20 20 mV
Force PWM mode, VOUT ≥ 1.0 V –2%  2%
PFM mode, VOUT ˂ 1.0 V, the average output voltage level is increased by max. 20 mV –20 40 mV
PFM mode, VOUT ≥ 1.0 V, the average output voltage level is increased by max. 20 mV –2% 2% + 20mV
Ripple voltage PWM mode, VOUT = 1.2 V, fSW = 4 MHz, COUT = 22 + 22 µF (GCM31CR71A226KE02) 5 mVp-p
PFM mode, L = 0.47 µH, COUT = 22 + 22 µF (GCM31CR71A226KE02) 25
DCLNR DC line regulation IOUT = IOUT(max) ±0.05 %/V
DCLDR DC load regulation in PWM mode VOUT_Bx = 1.0 V, IOUT from 0 to IOUT(max) 0.3%
TLDSR Transient load step response IOUT = 0 A to 3 A, TR = TF = 1 µs, PWM mode, VVIN_Bx = 3.3V, VOUT_Bx = 1.2 V, COUT = 22 + 22 µF, L = 0.47 µH, fSW = 4 MHz ±65 mV
TLNSR Transient line response V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±20 mV
ILIM FWD Forward current limit for both bucks (peak for every switching cycle) Programmable range 1.5 4.5 A
Step size 0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A –5% 7.5% 20%
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A –20% 7.5% 20%
ILIM NEG Negative current limit 1.6 2 3 A
RDS(ON) BUCK HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins (I = 1.0 A) 60 110
RDS(ON) BUCK LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins (I = 1.0 A) 55 80
ƒSW Switching frequency, PWM mode
OTP programmable
2-MHz setting or VOUT_Bx < 0.8 V 1.8 2 2.2 MHz
3-MHz setting and VOUT_Bx ≥ 0.8 V 2.7 3 3.3
4-MHz setting and VOUT_Bx ≥ 1.1 V 3.6 4 4.4
Start-up time (soft start) From ENx to VOUT_Bx = 0.35 V (slew-rate control begins) 120 µs
Overshoot during start-up 50 mV
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 010, VVOUT_Bx ≥ 0.7 V –15% 10 15% mV/µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 011, VVOUT_Bx ≥ 0.7 V –15% 7.5 15% mV/µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 100, VVOUT_Bx ≥ 0.7 V –15% 3.8 15% mV/µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 101, VVOUT_Bx ≥ 0.7 V –15% 1.9 15% mV/µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 110, VVOUT_Bx ≥ 0.7 V –15% 0.94 15% mV/µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 111, VVOUT_Bx ≥ 0.7 V –15% 0.47 15% mV/µs
IPFM-PWM PFM-to-PWM switch - current threshold(5) 520 mA
IPWM-PFM PWM-to-PFM switch - current threshold(5) 240 mA
Output pull-down resistance Converter disabled 75 125 175 Ω
BOOST CONVERTER
VIN_BST Input voltage range for boost power inputs 2.8 3.3 4 V
Input voltage range when bypass switch mode selected 4.5 5.5 V
VOUT_BST Output voltage, boost mode BOOST_VSET = 00 4.9 V
BOOST_VSET = 01 5.0
BOOST_VSET = 10 5.1
BOOST_VSET = 11 5.2
IOUT_BST Output current Both boost and bypass mode 0.6 A
ILIM_BST Output current limit BOOST_ILIM = 00, VIN_BST < 3.6 V 0.8 1 1.3 A
BOOST_ILIM = 01, VIN_BST < 3.6 V 1.1 1.4 1.9
BOOST_ILIM = 10, VIN_BST < 3.6 V 1.5 1.9 2.3
BOOST_ILIM = 11, VIN_BST < 3.6 V 2.2 2.8 3.4
VOUT_BST_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature. Boost mode Default output voltage –3% 3%
VDROP Voltage drop, bypass mode, Iout = 250 mA 83 mV
Ripple voltage, boost mode 22 µF effective output capacitance 20 mVp-p
DCLDR DC load regulation, boost mode IOUT = 1 mA to IOUT(max) 0.3%
TLDSR Transient load step response, boost mode IOUT = 1 mA to 250 mA, TR = TF = 1 µs, 22 µF effective output capacitance, VIN > 3 V –220 220 mV
ISHORT Short circuit current limitation During start-up, both boost and bypass mode. Short circuit current limit applies until VOUT_BST = VIN_BST 625 mA
RDS(ON) BST HS FET On-resistance, high-side FET Pin-to-pin, between SW_BST and VOUT_BST pins (I = 250 mA) 145 220
RDS(ON) BST LS FET On-resistance, low-side FET Pin-to-pin, between SW_BST and PGND_BST pins (I = 250 mA) 90 175
ƒSW Switching frequency, boost mode 2-MHz setting 1.8 2 2.2 MHz
4-MHz setting 3.6 4 4.4 MHz
Start-up time, boost mode From enable to boost VOUT within 3% of target value. COUT_BST = 22 µF 450 µs
Output pull-down resistance Converter disabled 135 Ω
EXTERNAL CLOCK AND PLL
External input clock(6) Nominal frequency 1 24 MHz
Nominal frequency step size 1
Required accuracy from nominal frequency –30% 10%
External clock detection Delay for detecting loss of external clock 1.8 µs
Delay for detecting valid external clock 20
Clock change delay (internal to external) Delay from valid clock detection to use of external clock 600 µs
PLL output clock jitter Cycle to cycle 300 ns, p-p
MONITORING FUNCTIONS
VANA Voltage Monitoring Voltage threshold, VANA_THRESHOLD = 0 3.3 V
Voltage threshold, VANA_THRESHOLD = 1 5.0
Voltage window, VANA_WINDOW = 00 +/-3% +/-4% +/-5%
Voltage window, VANA_WINDOW = 01 +/-4% +/-5% +/-6%
Voltage window, VANA_WINDOW = 10 or 11 +/-9% +/-10% +/-11%
VMON1 and VMON2 Voltage Monitoring Thresholds VMONx_THRESHOLD = 000 0.65 V
VMONx_THRESHOLD = 001 0.8
VMONx_THRESHOLD = 010 1.0
VMONx_THRESHOLD = 011 1.1
VMONx_THRESHOLD = 100 1.2
VMONx_THRESHOLD = 101 1.3
VMONx_THRESHOLD = 110 1.8
VMONx_THRESHOLD = 111 1.8
VMON1 and VMON2 Voltage Monitoring Windows VMONx_WINDOW = 00 +/-1% +/-2% +/-3%
VMONx_WINDOW = 01 +/-2% +/-3% +/-4%
VMONx_WINDOW = 10 +/-3% +/-4% +/-5%
VMONx_WINDOW = 11 +/-5% +/-6% +/-7%
Buck0 and Buck1 Voltage Monitoring Windows BUCKx_WINDOW = 00 +/-20 +/-30 +/-40 mV
BUCKx_WINDOW = 01 +/-37 +/-50 +/-63
BUCKx_WINDOW = 10 +/-57 +/-70 +/-83
BUCKx_WINDOW = 11 +/-77 +/-90 +/-103
Boost Voltage Monitoring BOOST_WINDOW = 00 +/-0.6% +/-2% +/-3.4%
BOOST_WINDOW = 01 +/-2.6% +/-4% +/-5.4%
BOOST_WINDOW = 10 +/-4.6% +/-6% +/-7.4%
BOOST_WINDOW = 11 +/-6.6% +/-8% +/-9.4%
Deglitch time VANA, VMONx and BOOST monitoring 12 17 μs
BUCKx monitoring 6 9
PROTECTION FUNCTIONS
Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °C
Temperature rising, TDIE_WARN_LEVEL = 1 130 140 150
Hysteresis 20
Thermal shutdown Temperature rising 140 150 160 °C
Hysteresis 20
VANAOVP VANA Overvoltage Voltage rising, VANA_OVP_SEL = 0 5.6 5.8 6.1 V
Voltage falling, VANA_OVP_SEL = 0 5.45 5.73 5.96
Voltage rising, VANA_OVP_SEL = 1 4.1 4.3 4.6
Voltage falling, VANA_OVP_SEL = 1 3.95 4.23 4.46
Hysteresis 40 200 mV
VANAUVLO VANA Undervoltage Lockout Voltage rising 2.51 2.63 2.75 V
Voltage falling 2.5 2.6 2.7
BUCKx short circuit detection Threshold 0.32 0.35 0.45 V
Bypass short circuit current limit 270 420 mA
LOAD CURRENT MEASUREMENT FOR BUCK CONVERTERS
Current measurement range Maximum code 10.22 A
Resolution LSB 20 mA
Measurement accuracy IOUT > 1A <10%
Measurement time Auto mode (automatically changing to PWM mode for the measurement) 50 µs
PWM mode 4
CURRENT CONSUMPTION
Shutdown current consumption NRST = 0 1 µA
Standby current consumption, converters disabled NRST = 1 9 µA
Active current consumption, one buck converter enabled in Auto mode, internal RC oscillator IOUT_Bx = 0 mA, not switching 55 µA
Active current consumption, two buck converters enabled in Auto mode, internal RC oscillator IOUT_Bx = 0 mA, not switching 90 µA
Active current consumption during PWM operation, one buck converter enabled IOUT_Bx = 0 mA 15 mA
Active current consumption during PWM operation, two buck converters enabled IOUT_Bx = 0 mA 27 mA
Active current consumption, Boost converter in PWM operation IOUT_BST = 0 mA, fSW = 4 MHz 18 mA
PLL and clock detector current consumption Additional current consumption when enabled, 2 MHz external clock 2 mA
DIGITAL INPUT SIGNALS SCL, SDA, NRST, EN1, EN2, EN3, CLKIN,
WDI
VIL Input low level 0.4 V
VIH Input high level 1.2
VHYS Hysteresis of Schmitt Trigger inputs 10 80 200 mV
ENx, CLKIN, WDI pull-down resistance ENx_PD = 1, CLKIN_PD = 1, WDI_PD = 1 500
NRST pull-down resistance Always enabled 500
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL Output low level SDA: ISOURCE = 20 mA 0.5 V
nINT: ISOURCE = 2 mA 0.4
RP External pull-up resistor for nINT To VIO Supply 10 kΩ
DIGITAL OUTPUT SIGNALS PGOOD, PG1, GPO0, GPO1, GPO2,
WD_RESET
VOL Output low level ISOURCE = 2 mA 0.4 V
VOH Output high level, configured to push-pull ISINK = 2 mA VVANA - 0.4 VVANA
VPU Supply voltage for external pull-up resistor, configured to open-drain VVANA
RPU External pull-up resistor, configured to open-drain 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs except NRST, over pin voltage range, when PD not enabled −1 1 µA
NRST, over pin voltage range. Other logic inputs when PD enabled. –1 20 µA
All voltage values are with respect to network ground.
Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.
The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. Applies when internal oscillator is used.
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the inductor current level.
The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.