ZHCSH72I September 2011 – December 2017 LMK00301
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
DAP | DAP | GND | Die Attach Pad. Connect to the PCB ground plane for heat dissipation. |
1, 2 | CLKoutA0, CLKoutA0* | O | Differential clock output A0. Output type set by CLKoutA_TYPE pins. |
3, 4 | CLKoutA1, CLKoutA1* | O | Differential clock output A1. Output type set by CLKoutA_TYPE pins. |
5, 8 | VCCOA | PWR | Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1) |
6, 7 | CLKoutA2, CLKoutA2* | O | Differential clock output A2. Output type set by CLKoutA_TYPE pins. |
9, 10 | CLKoutA3, CLKoutA3* | O | Differential clock output A3. Output type set by CLKoutA_TYPE pins. |
11, 12 | CLKoutA4, CLKoutA4* | O | Differential clock output A4. Output type set by CLKoutA_TYPE pins. |
13, 18, 24, 37, 43, 48 | GND | GND | Ground |
14, 47 | CLKoutA_TYPE0, CLKoutA_TYPE1 | I | Bank A output buffer type selection pins (2) |
15, 42 | Vcc | PWR | Power supply for Core and Input Buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin. |
16 | OSCin | I | Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock. |
17 | OSCout | O | Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock. |
19, 22 | CLKin_SEL0, CLKin_SEL1 | I | Clock input selection pins (2) |
20, 21 | CLKin0, CLKin0* | I | Universal clock input 0 (differential/single-ended) |
23, 39 | CLKoutB_TYPE0, CLKoutB_TYPE1 | I | Bank B output buffer type selection pins (2) |
25, 26 | CLKoutB4*, CLKoutB4 | O | Differential clock output B4. Output type set by CLKoutB_TYPE pins. |
27, 28 | CLKoutB3*, CLKoutB3 | O | Differential clock output B3. Output type set by CLKoutB_TYPE pins. |
29, 32 | VCCOB | PWR | Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1) |
30, 31 | CLKoutB2*, CLKoutB2 | O | Differential clock output B2. Output type set by CLKoutB_TYPE pins. |
33, 34 | CLKoutB1*, CLKoutB1 | O | Differential clock output B1. Output type set by CLKoutB_TYPE pins. |
35, 36 | CLKoutB0*, CLKoutB0 | O | Differential clock output B0. Output type set by CLKoutB_TYPE pins. |
38 | NC | — | Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in Absolute Maximum Ratings. |
40, 41 | CLKin1*, CLKin1 | I | Universal clock input 1 (differential/single-ended) |
44 | REFout | O | LVCMOS reference output. Enable output by pulling REFout_EN pin high. |
45 | VCCOC | PWR | Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1) |
46 | REFout_EN | I | REFout enable input. Enable signal is internally synchronized to selected clock input. (2) |