ZHCSH72I September   2011  – December 2017 LMK00301

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      功能框图
      2.      LVPECL 输出摆幅 (VOD) 与频率间的关系
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
      2. 9.3.2 Clock Inputs
      3. 9.3.3 Clock Outputs
        1. 9.3.3.1 Reference Output
  10. 10Application and Implementation
    1. 10.1 Driving the Clock Inputs
    2. 10.2 Crystal Interface
    3. 10.3 Termination and Use of Clock Drivers
      1. 10.3.1 Termination for DC Coupled Differential Operation
      2. 10.3.2 Termination for AC Coupled Differential Operation
      3. 10.3.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate Vcc and Vcco Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

48-Pin WQFN
Package RHS0048A
Top View
LMK00301 30147002.gif

Pin Functions(3)

PINTYPEDESCRIPTION
NO.NAME
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
1, 2 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins.
3, 4 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins.
5, 8 VCCOA PWR Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
6, 7 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins.
9, 10 CLKoutA3, CLKoutA3* O Differential clock output A3. Output type set by CLKoutA_TYPE pins.
11, 12 CLKoutA4, CLKoutA4* O Differential clock output A4. Output type set by CLKoutA_TYPE pins.
13, 18, 24, 37, 43, 48 GND GND Ground
14, 47 CLKoutA_TYPE0, CLKoutA_TYPE1 I Bank A output buffer type selection pins (2)
15, 42 Vcc PWR Power supply for Core and Input Buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin.
16 OSCin I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
17 OSCout O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
19, 22 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (2)
20, 21 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended)
23, 39 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B output buffer type selection pins (2)
25, 26 CLKoutB4*, CLKoutB4 O Differential clock output B4. Output type set by CLKoutB_TYPE pins.
27, 28 CLKoutB3*, CLKoutB3 O Differential clock output B3. Output type set by CLKoutB_TYPE pins.
29, 32 VCCOB PWR Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
30, 31 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins.
33, 34 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins.
35, 36 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins.
38 NC — Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in Absolute Maximum Ratings.
40, 41 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended)
44 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
45 VCCOC PWR Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
46 REFout_EN I REFout enable input. Enable signal is internally synchronized to selected clock input. (2)
(1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.
(2) CMOS control input with internal pull-down resistor.
(3) Any unused output pin should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration and Termination and Use of Clock Drivers for output interface and termination techniques.