ZHCSH72I September   2011  – December 2017 LMK00301

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能框图
      2.      LVPECL 输出摆幅 (VOD) 与频率间的关系
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
      2. 9.3.2 Clock Inputs
      3. 9.3.3 Clock Outputs
        1. 9.3.3.1 Reference Output
  10. 10Application and Implementation
    1. 10.1 Driving the Clock Inputs
    2. 10.2 Crystal Interface
    3. 10.3 Termination and Use of Clock Drivers
      1. 10.3.1 Termination for DC Coupled Differential Operation
      2. 10.3.2 Termination for AC Coupled Differential Operation
      3. 10.3.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate Vcc and Vcco Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver, it is important to ensure the receiver is biased to its ideal DC level.

When driving differential receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors; however the proper DC bias point needs to be established at both the driver side and the receiver side. The recommended termination scheme depends on whether the differential receiver has integrated termination resistors or not.

When driving a differential receiver without internal 100 Ω differential termination, the AC coupling capacitors should be placed between the load termination resistor and the receiver to allow a DC path for proper biasing of the LVDS driver. This is shown in Figure 33. The load termination resistor and AC coupling capacitors should be placed as close as possible to the receiver inputs to minimize stub length. The receiver can be biased internally or externally to a reference voltage within the receiver’s common mode input range through resistors in the kilo-ohm range.

When driving a differential receiver with internal 100 Ω differential termination, a source termination resistor should be placed before the AC coupling capacitors for proper DC biasing of the driver as shown in Figure 34. However, with a 100 Ω resistor at the source and the load (i.e. double terminated), the equivalent resistance seen by the LVDS driver is 50 Ω which causes the effective signal swing at the input to be reduced by half. If a self-terminated receiver requires input swing greater than 250 mVpp (differential) as well as AC coupling to its inputs, then the LVDS driver with the double-terminated arrangement in Figure 34 may not meet the minimum input swing requirement; alternatively, the LVPECL or HCSL output driver format with AC coupling is recommended to meet the minimum input swing required by the self-terminated receiver.

When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The examples in Figure 33 and Figure 34 use 0.1 μF capacitors, but this value may be adjusted to meet the startup requirements for the particular application.

LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 160 Ω emitter resistors (or 91 Ω for Vcco = 2.5 V) close to the LVPECL driver to provide a DC path to ground as shown in Figure 38. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. Alternatively, a Thevenin equivalent circuit forms a valid termination as shown in Figure 35 for Vcco = 3.3 V and 2.5 V. Note: this Thevenin circuit is different from the DC coupled example in Figure 32, since the voltage divider is setting the input common mode voltage of the receiver.

LMK00301 30147024.gifFigure 35. Differential LVPECL Operation, AC Coupling,
Thevenin Equivalent