ZHCSID5E April   2018  – September 2019 ISO1410 , ISO1412 , ISO1430 , ISO1432 , ISO1450 , ISO1452

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化应用电路原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: Full-Duplex Device
    2.     Pin Functions: Half-Duplex Device
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Power Ratings
    6. 8.6  Insulation Specifications
    7. 8.7  Safety-Related Certifications
    8. 8.8  Safety Limiting Values
    9. 8.9  Electrical Characteristics: Driver
    10. 8.10 Electrical Characteristics: Receiver
    11. 8.11 Supply Current Characteristics: Side 1 (ICC1)
    12. 8.12 Supply Current Characteristics: Side 2 (ICC2)
    13. 8.13 Switching Characteristics: Driver
    14. 8.14 Switching Characteristics: Receiver
    15. 8.15 Insulation Characteristics Curves
    16. 8.16 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 10.3.2 Failsafe Receiver
      3. 10.3.3 Thermal Shutdown
      4. 10.3.4 Glitch-Free Power Up and Power Down
    4. 10.4 Device Functional Modes
      1. 10.4.1 Device I/O Schematics
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Data Rate and Bus Length
        2. 11.2.2.2 Stub Length
        3. 11.2.2.3 Bus Loading
      3. 11.2.3 Application Curves
        1. 11.2.3.1 Insulation Lifetime
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 PCB Material
    2. 13.2 Layout Example
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档
    2. 14.2 相关链接
    3. 14.3 接收文档更新通知
    4. 14.4 社区资源
    5. 14.5 商标
    6. 14.6 静电放电警告
    7. 14.7 Glossary
  15. 15机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DW|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
DW-16
IEC 60664-1
CLR External clearance (1) Side 1 to side 2 distance through air >8 mm
CPG External creepage (1) Side 1 to side 2 distance across package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 56 1060 VRMS
DC voltage 1500 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7071 VPK
VIOSM Maximum surge isolation voltage
ISO141x (3) 		Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 10000 VPK (qualification) 6250 VPK
Maximum surge isolation voltage
ISO141xB (3) 		Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 6000 VPK (qualification) 4615 VPK
qpd Apparent charge (4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
ISO14xx: Vpd(m) = 1.6 × VIORM , tm = 10 s
ISO14xxB: Vpd(m) = 1.2 × VIORM , tm = 10 s		 ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
ISO14xx: Vpd(m) = 1.875 × VIORM , tm = 1 s
ISO14xxB: Vpd(m) = 1.5 × VIORM , tm = 1 s		 ≤ 5
CIO Barrier capacitance, input to output (5) VIO = 0.4 × sin (2 πft), f = 1 MHz 1 pF
RIO Insulation resistance, input to output (5) VIO = 500 V,  TA = 25°C > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 150°C > 1011
VIO = 500 V at  TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/
21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification);
VTEST = 1.2 × VISO , t = 1 s (100% production)		 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO14xx is suitable for safe electrical insulation and ISO14xxB is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.