ZHCS321I June   2009  – January 2015 ISO1050

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Supply Current
    6. 6.6  Electrical Characteristics: Driver
    7. 6.7  Electrical Characteristics: Receiver
    8. 6.8  Switching Characteristics: Device
    9. 6.9  Switching Characteristics: Driver
    10. 6.10 Switching Characteristics: Receiver
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CAN Bus States
      2. 8.3.2 Digital Inputs and Outputs
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant Time-Out (DTO)
        2. 8.3.3.2 Thermal Shutdown
        3. 8.3.3.3 Undervoltage Lockout and Fail-Safe
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
        2. 9.2.2.2 CAN Termination
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DUB|8
  • DW|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Parameter Measurement Information

ISO1050 dvr_v_tst_lls983.gifFigure 7. Driver Voltage, Current and Test Definitions
ISO1050 bus_logic_lls983.gifFigure 8. Bus Logic State Voltage Definitions
ISO1050 dvr_vod_lls983.gifFigure 9. Driver VOD With Common-Mode Loading Test Circuit
ISO1050 dvr_tst_cir_lls983.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 10. Driver Test Circuit and Voltage Waveforms
ISO1050 rec_v_lls983.gifFigure 11. Receiver Voltage and Current Definitions
ISO1050 rec_tst_cir_lls983.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 12. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L VOL
12 V 11.1 V 900 mV L
–6 V –12 V 6 V L
12 V 6 V 6 V L
–11.5 V –12 V 500 mV H VOH
12 V 11.5 V 500 mV H
–12 V –6 V –6 V H
6 V 12 V –6 V H
Open Open X H
ISO1050 over_v_tst_lls983.gifFigure 13. Transient Overvoltage Test Circuit
ISO1050 p_p_vo_tst_lls983.gifFigure 14. Peak-to-Peak Output Voltage Test Circuit and Waveform
ISO1050 tloop_tst_cir_lls983.gifFigure 15. tLOOP Test Circuit and Voltage Waveforms
ISO1050 timeout_tst_lls983.gif
A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 16. Dominant Time-out Test Circuit and Voltage Waveforms
ISO1050 dvr_short_cir_lls983.gifFigure 17. Driver Short-Circuit Current Test Circuit and Waveforms
ISO1050 failsafe_lls983.gifFigure 18. Fail-Safe Delay Time Test Circuit and Voltage Waveforms
ISO1050 comm_mode_lls983.gifFigure 19. Common-Mode Transient Immunity Test Circuit
ISO1050 meas_setup_lls983.gifFigure 20. Electromagnetic Emissions Measurement Setup