at TA = 25°C,
VS = (V+) – (V–) = 5.5 V, VIN = (VIN+) –
(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF,
VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2
and G = 10 (unless otherwise noted)
![INA351 Typical Distribution of Input Referred Offset Voltage GUID-20230131-SS0I-SG7S-KZQT-MK4SVSBQQSNR-low.gif](/ods/images/ZHCSR64C/GUID-20230131-SS0I-SG7S-KZQT-MK4SVSBQQSNR-low.gif)
G = 10, 20, 30, 50 |
N = 36 |
μ = 23 μV |
σ = 0.180 mV |
Figure 7-1 Typical Distribution of Input Referred Offset Voltage![INA351 Typical Distribution of Input Bias Current GUID-20221130-SS0I-R5QX-DS8L-3RGGBWWZV4RF-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-R5QX-DS8L-3RGGBWWZV4RF-low.gif)
TA = 25°C |
N = 72 |
μ = 0.33 pA |
σ = 0.43 pA |
Figure 7-3 Typical Distribution of Input Bias Current ![INA351 Typical Distribution of Input Bias Current GUID-20221130-SS0I-0PZB-BGBH-74QBLP1RHZF7-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-0PZB-BGBH-74QBLP1RHZF7-low.gif)
TA = 85°C |
N = 72 |
μ = 3.3 pA |
σ = 0.53 pA |
Figure 7-5 Typical Distribution of Input Bias Current ![INA351 Typical Distribution of CMRR GUID-20221130-SS0I-HWDN-V2MW-W1VFD2ZD23KJ-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-HWDN-V2MW-W1VFD2ZD23KJ-low.gif)
G = 10 |
N = 36 |
μ = -0.30 μV/V |
σ = 7.10 μV/V |
Figure 7-7 Typical Distribution of CMRR ![INA351 Typical Distribution of CMRR GUID-20230131-SS0I-H5DC-DF4G-VBM7G5VST8HM-low.gif](/ods/images/ZHCSR64C/GUID-20230131-SS0I-H5DC-DF4G-VBM7G5VST8HM-low.gif)
G = 30 |
N = 36 |
μ = –1.23 μV/V |
σ = 7.52 μV/V |
Figure 7-9 Typical Distribution of CMRR ![INA351 Typical Distribution of Gain
Error GUID-20221130-SS0I-K7XN-JTGB-NZDWWC1STRSG-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-K7XN-JTGB-NZDWWC1STRSG-low.gif)
G = 10 |
N = 36 |
μ = 0.002 % |
σ = 0.02 % |
Figure 7-11 Typical Distribution of Gain
Error ![INA351 Typical Distribution of Gain Error GUID-20230201-SS0I-KFGK-2PTQ-4JJSKJXJMHZW-low.gif](/ods/images/ZHCSR64C/GUID-20230201-SS0I-KFGK-2PTQ-4JJSKJXJMHZW-low.gif)
G = 30 |
N = 36 |
μ = 0.0067 % |
σ = 0.011 % |
Figure 7-13 Typical Distribution of Gain Error
Figure 7-15 Input
Referred Offset Voltage vs Temperature
Figure 7-17 Input
Offset Current vs Temperature
Figure 7-19 Shutdown Quiescent Current vs Temperature
Figure 7-21 Gain
Error vs Temperature![INA351 Input
Referred Offset Voltage vs Input Common-Mode Voltage GUID-20221130-SS0I-2QZC-8PBS-VQTHBNSBGQGS-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-2QZC-8PBS-VQTHBNSBGQGS-low.gif)
V+ =
2.75 V and V– = –2.75 V |
Figure 7-23 Input
Referred Offset Voltage vs Input Common-Mode Voltage![INA351 Input
Bias Current vs Input Common-Mode Voltage GUID-20221130-SS0I-X0HH-T0GV-XTRQPGSFTB37-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-X0HH-T0GV-XTRQPGSFTB37-low.gif)
V+ =
2.75 V and V– = –2.75 V |
Figure 7-25 Input
Bias Current vs Input Common-Mode Voltage![INA351 Quiescent Current vs Input Common-Mode Voltage GUID-20221130-SS0I-9FPR-JBWW-BKMCH4BNRWCN-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-9FPR-JBWW-BKMCH4BNRWCN-low.gif)
V+ =
2.75 V and V– = –2.75 V |
Figure 7-27 Quiescent Current vs Input Common-Mode Voltage
Figure 7-29 Quiescent Current vs Supply Voltage
Figure 7-31 Output Voltage vs Output Current (Sinking)
Figure 7-33 CMRR
(Referred to Input) vs Frequency
Figure 7-35 PSRR–
(Referred to Input) Vs Frequency
Figure 7-37 0.1
Hz to 10 Hz Voltage Noise in Time Domain
Figure 7-39 Maximum Output Voltage vs Frequency![INA351 THD + N Frequency GUID-20221129-SS0I-8KZG-TT6X-NZHHL0LVNXMH-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-8KZG-TT6X-NZHHL0LVNXMH-low.gif)
VS = 5.5 V |
BW = 80 kHz |
VCM = 2.75 V |
RL = 100 kΩ |
VOUT = 1
VRMS |
|
Figure 7-41 THD + N Frequency![INA351 Small-Signal Overshoot vs
Capacitive Load GUID-20221129-SS0I-7DLW-TBML-F90Z1H45RPXX-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-7DLW-TBML-F90Z1H45RPXX-low.gif)
VS = 5.5 V |
G = 10 |
VOUT = 100
mVPP |
Figure 7-43 Small-Signal Overshoot vs
Capacitive Load![INA351 Small-Signal Overshoot vs Capacitive Load GUID-20221129-SS0I-GNCC-HC9N-WNMWMBQLM8BH-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-GNCC-HC9N-WNMWMBQLM8BH-low.gif)
VS = 5.5 V |
G = 30 |
VOUT = 100
mVPP |
Figure 7-45 Small-Signal Overshoot vs Capacitive Load![INA351 Large
Signal Step Response GUID-20221130-SS0I-WTPH-8MVJ-BDXCXZ4WHJJW-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-WTPH-8MVJ-BDXCXZ4WHJJW-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VOUT = 2
VPP |
Figure 7-47 Large
Signal Step Response![INA351 Large Signal Settling Time
(Rising Edge) GUID-20221129-SS0I-K21Q-ZQR5-6NVXWQ926K4M-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-K21Q-ZQR5-6NVXWQ926K4M-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VOUT = 2
VPP |
Figure 7-49 Large Signal Settling Time
(Rising Edge)![INA351 Small-Signal Step
Response GUID-20221129-SS0I-BLH6-SW9C-CHFPZBW9GW70-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-BLH6-SW9C-CHFPZBW9GW70-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VOUT = 0.1
VPP |
Figure 7-51 Small-Signal Step
Response![INA351 Over-Load Recovery (Rising Edge) GUID-20221129-SS0I-V47L-GDDT-XWNGPRXQDMX1-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-V47L-GDDT-XWNGPRXQDMX1-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VIN = 1
VPP |
Figure 7-53 Over-Load Recovery (Rising Edge)![INA351 No
Phase Reversal GUID-20221129-SS0I-1RCK-1SLP-NZKD0DNLMP7W-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-1RCK-1SLP-NZKD0DNLMP7W-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VIN = 0.6
VPP |
Figure 7-55 No
Phase Reversal![INA351 Disable Response GUID-20221129-SS0I-X4MW-BFMN-G7NHLWML57K1-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-X4MW-BFMN-G7NHLWML57K1-low.gif)
V+ = +2.75 V |
V– = –2.75 V |
G = 10 |
Figure 7-57 Disable Response![INA351 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region) GUID-20221130-SS0I-MVSP-M5Q2-XQQ6HDV4QLXP-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-MVSP-M5Q2-XQQ6HDV4QLXP-low.gif)
VS = 5.5 V |
G = 10, 20, 30, 50 |
VREF = VS / 2 |
Figure 7-59 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region)![INA351 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region) GUID-20221130-SS0I-S0DB-XDP8-XTQJKR0SQBV4-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-S0DB-XDP8-XTQJKR0SQBV4-low.gif)
VS = 5.5 V |
G = 10, 20, 30, 50 |
VREF = 0 V |
Figure 7-61 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region)![INA351 Input
Common-Mode Voltage vs Output Voltage GUID-20221130-SS0I-7JPT-CRNW-S7SPW3N1B2NF-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-7JPT-CRNW-S7SPW3N1B2NF-low.gif)
VS = 5.5 V |
G = 10, 20, 30, 50 |
VREF = VS / 2 |
Figure 7-63 Input
Common-Mode Voltage vs Output Voltage![INA351 Input Common-Mode Voltage vs
Output Voltage GUID-20221130-SS0I-VMCT-BKHS-BKLLF6Z9XBQ3-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-VMCT-BKHS-BKLLF6Z9XBQ3-low.gif)
VS = 5.5 V |
G = 10, 20, 30, 50 |
VREF = 0 V |
Figure 7-65 Input Common-Mode Voltage vs
Output Voltage![INA351 Typical Distribution of Input Referred Offset Drift GUID-20230131-SS0I-K909-FFBL-4FKDSZXW7KH9-low.gif](/ods/images/ZHCSR64C/GUID-20230131-SS0I-K909-FFBL-4FKDSZXW7KH9-low.gif)
G = 10, 20, 30, 50 |
N = 36 |
μ = 0.23 μV/°C |
σ = 0.36 μV/°C |
Figure 7-2 Typical Distribution of Input Referred Offset Drift![INA351 Typical Distribution of Input Offset Current GUID-20221130-SS0I-6QPH-FG3T-4LVTCLXK61DV-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-6QPH-FG3T-4LVTCLXK61DV-low.gif)
TA = 25°C |
N = 36 |
μ = –0.40 pA |
σ = 0.47 pA |
Figure 7-4 Typical Distribution of Input Offset Current ![INA351 Typical Distribution of Input Offset Current GUID-20221130-SS0I-Z7ML-PV4C-JBSVH3M7QH1H-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-Z7ML-PV4C-JBSVH3M7QH1H-low.gif)
TA = 85°C |
N = 36 |
μ = 0.05 pA |
σ = 0.30 pA |
Figure 7-6 Typical Distribution of Input Offset Current ![INA351 Typical Distribution of CMRR GUID-20221130-SS0I-ZKRH-TVGV-R2HGKD4M1LPX-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-ZKRH-TVGV-R2HGKD4M1LPX-low.gif)
G = 20 |
N = 36 |
μ = -0.27 μV/V |
σ = 7.20 μV/V |
Figure 7-8 Typical Distribution of CMRR ![INA351 Typical Distribution of CMRR GUID-20230131-SS0I-BQWT-NJM5-KSXDQD9HBVSD-low.gif](/ods/images/ZHCSR64C/GUID-20230131-SS0I-BQWT-NJM5-KSXDQD9HBVSD-low.gif)
G = 50 |
N = 36 |
μ = –1.16 μV/V |
σ = 7.62 μV/V |
Figure 7-10 Typical Distribution of CMRR ![INA351 Typical Distribution of Gain Error GUID-20221130-SS0I-98BS-VBBB-9BRWVPRGJSHP-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-98BS-VBBB-9BRWVPRGJSHP-low.gif)
G = 20 |
N = 36 |
μ = -0.02 % |
σ = 0.02 % |
Figure 7-12 Typical Distribution of Gain Error ![INA351 Typical Distribution of Gain Error GUID-20230201-SS0I-VVDV-PX06-CQFRLKBX7XQP-low.gif](/ods/images/ZHCSR64C/GUID-20230201-SS0I-VVDV-PX06-CQFRLKBX7XQP-low.gif)
G = 50 |
N = 36 |
μ = 0.0035 % |
σ = 0.012 % |
Figure 7-14 Typical Distribution of Gain Error
Figure 7-16 Input
Bias Current vs Temperature
Figure 7-18 Quiescent Current vs Temperature
Figure 7-20 Short
Circuit Current vs Temperature
Figure 7-22 CMRR
vs Temperature![INA351 Input
Referred Offset Voltage vs Input Common-Mode Voltage GUID-20221130-SS0I-Z13B-JVP1-G5CBM3BGG9ZF-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-Z13B-JVP1-G5CBM3BGG9ZF-low.gif)
V+ =
1.65 V and V– = –1.65 V |
Figure 7-24 Input
Referred Offset Voltage vs Input Common-Mode Voltage![INA351 Input
Offset Current vs Input Common-Mode Voltage GUID-20221130-SS0I-S4FL-WSRZ-4XV8MD3RZRGQ-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-S4FL-WSRZ-4XV8MD3RZRGQ-low.gif)
V+ =
2.75 V and V– = –2.75 V |
Figure 7-26 Input
Offset Current vs Input Common-Mode Voltage
Figure 7-28 Input
Referred Offset Voltage vs Supply Voltage
Figure 7-30 Output Voltage vs Output Current (Sourcing)
Figure 7-32 Closed-Loop Gain vs Frequency
Figure 7-34 PSRR+
(Referred to Input) vs Frequency
Figure 7-36 Input
Referred Voltage Noise Spectral Density
Figure 7-38 Closed-Loop Output Impedance vs Frequency![INA351 THD +
N Frequency GUID-20221129-SS0I-WZFQ-FPVD-1TK0VPSP06ZB-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-WZFQ-FPVD-1TK0VPSP06ZB-low.gif)
VS = 5.5 V |
BW = 80 kHz |
VCM = 2.75 V |
RL = 10 kΩ |
VOUT = 0.5
VRMS |
|
Figure 7-40 THD +
N Frequency
Figure 7-42 Electromagnetic Interference
Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency![INA351 Small-Signal Overshoot vs
Capacitive Load GUID-20221129-SS0I-MDKL-1NVB-XLLHVHPHVRVJ-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-MDKL-1NVB-XLLHVHPHVRVJ-low.gif)
VS = 5.5 V |
G = 20 |
VOUT = 100
mVPP |
Figure 7-44 Small-Signal Overshoot vs
Capacitive Load![INA351 Small-Signal Overshoot vs Capacitive Load GUID-20221129-SS0I-VK30-QZDQ-JLT13DZZXCVF-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-VK30-QZDQ-JLT13DZZXCVF-low.gif)
VS = 5.5 V |
G = 50 |
VOUT = 100
mVPP |
Figure 7-46 Small-Signal Overshoot vs Capacitive Load![INA351 Large Signal Settling Time
(Falling Edge) GUID-20221129-SS0I-NLFG-XCHQ-QHPW43QTSN6Z-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-NLFG-XCHQ-QHPW43QTSN6Z-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VOUT = 2
VPP |
Figure 7-48 Large Signal Settling Time
(Falling Edge)![INA351 Large Signal Step
Response GUID-20221130-SS0I-PWZS-4QL3-TKMRL3SKX9JK-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-PWZS-4QL3-TKMRL3SKX9JK-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 50 |
VOUT = 2
VPP |
Figure 7-50 Large Signal Step
Response![INA351 Small-Signal Step Response GUID-20221129-SS0I-C3QQ-N2C5-JDKRXJNFMZBS-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-C3QQ-N2C5-JDKRXJNFMZBS-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 50 |
VOUT = 0.1
VPP |
Figure 7-52 Small-Signal Step Response![INA351 Over-Load Recovery (Falling Edge) GUID-20221129-SS0I-1VVF-CL9D-PVJNRQWJWD00-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-1VVF-CL9D-PVJNRQWJWD00-low.gif)
V+ = 2.75 V |
V– = –2.75 V |
G = 10 |
VIN = 1
VPP |
Figure 7-54 Over-Load Recovery (Falling Edge)![INA351 Enable Response GUID-20221129-SS0I-M0MV-CZWC-0BTX4FXB9FVS-low.gif](/ods/images/ZHCSR64C/GUID-20221129-SS0I-M0MV-CZWC-0BTX4FXB9FVS-low.gif)
V+ = +2.75 V |
V– = –2.75 V |
G = 10 |
Figure 7-56 Enable Response![INA351 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region) GUID-20221130-SS0I-SCMW-NT7Q-GB4XDDN6GNG5-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-SCMW-NT7Q-GB4XDDN6GNG5-low.gif)
VS = 3.3 V |
G = 10, 20, 30, 50 |
VREF = VS / 2 |
Figure 7-58 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region)![INA351 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region) GUID-20221130-SS0I-N59F-9WG9-MQW2JRSVPR1K-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-N59F-9WG9-MQW2JRSVPR1K-low.gif)
VS = 3.3 V |
G = 10, 20, 30, 50 |
VREF = 0 V |
Figure 7-60 Input
Common-Mode Voltage vs Output Voltage (High CMRR Region)![INA351 Input
Common-Mode Voltage vs Output Voltage GUID-20221130-SS0I-HJFJ-X09X-HNWB5C5NWNBF-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-HJFJ-X09X-HNWB5C5NWNBF-low.gif)
VS = 3.3 V |
G = 10, 20, 30, 50 |
VREF = VS / 2 |
Figure 7-62 Input
Common-Mode Voltage vs Output Voltage![INA351 Input Common-Mode Voltage vs
Output Voltage GUID-20221130-SS0I-3X3B-2WRR-F6HH9VV7RWSD-low.gif](/ods/images/ZHCSR64C/GUID-20221130-SS0I-3X3B-2WRR-F6HH9VV7RWSD-low.gif)
VS = 3.3 V |
G = 10, 20, 30, 50 |
VREF = 0 V |
Figure 7-64 Input Common-Mode Voltage vs
Output Voltage