ZHCSEX8A December 2015 – October 2016 INA300-Q1
The INA300-Q1 is a 36-V, common-mode comparator designed for overcurrent protection applications. To reduce the system component count, this device combines the current-sense amplifier and threshold comparison into a single product for the overcurrent detection function. Programming this comparison threshold is configured through a single external resistor, which simplifies the current design while allowing for easy adjustments to the threshold when needed. The threshold setting resistor value is selected based on an internal 20-µA current source to achieve a corresponding signal to the voltage that develops across the current-sensing or current-shunt resistor in series with the monitored load current.
The device is designed to accommodate a range of application requirements, including common-mode voltage, noise thresholds, and signal ranges. A wide signal threshold range reaching up to 250 mV is available to accommodate both power-sensitive applications requiring small dissipations across a current sense resistor and larger current-sensing resistors used in lower current applications.
Additional features available with the INA300-Q1 device include a disable mode for reducing the current consumption of the device to below 10 µA, an output mode selector to enable a latched or transparent alert output, and a selectable hysteresis value and alert response delay.
The wide signal range of the device is further enhanced with an adjustable hysteresis value to adjust the characteristics of the comparator, which allows for better accommodation of the full input range. The selectable alert response delays present in the INA300-Q1 device assist in optimizing device operation to account for the system noise levels and operating characteristics required from this device. Longer delay settings allow for added rejection of system noise, thus reducing the potential for false alerts resulting from noise spikes that can occur in high-speed comparators.
The device measures the differential voltage developed across a resistor when current flows through it to determine if the monitored current exceeds a defined limit. This resistor is referred to as a current-sensing resistor or a current-shunt resistor, with each term used interchangeably. The flexible design of the device allows for measuring a wide differential input signal range across this current-sensing resistor, which can extend up to 250 mV.
Selecting the value of this current-sensing resistor is based primarily on two factors: the required accuracy of the current measurement and the allowable power dissipation across the current-sensing resistor. Larger voltages developed across this resistor allow more accurate measurements. This large signal accuracy improvement results from the fixed internal amplifier errors that are dominated by the inherent input offset voltage of the device. When the input signal decreases, these fixed internal amplifier errors become a larger portion of the measurement and increase the uncertainty in the measurement accuracy. When the input signal increases, the measurement uncertainty is reduced because the fixed errors are a smaller percentage of measured signal.
A system design trade-off for improving the measurement accuracy using larger input signals is the increase in power across the current-sensing resistor. Increasing the value of the current-shunt resistor increases the differential voltage developed across the resistor when current passes through the component. This increase in voltage across the resistor increases the power that the resistor must be able to dissipate. Decreasing the value of the current-shunt resistor value reduces the power dissipation requirements of the resistor, but increases the measurement errors resulting from the decreased input signal. Selecting the optimal value for the shunt resistor requires factoring both the accuracy requirement for the specific application and the allowable power dissipation of this component.
An increasing number of low ohmic-value resistors are becoming available with values as low as 200 µΩ, with power dissipations of up to 5 W that enable large currents to be monitored with sensing resistors.
In this example, the trade-offs involved in selecting a current-sensing resistor are discussed. This example requires a 5% measurement accuracy for detecting a 10-A overcurrent event at a 50-µs delay setting where only 250 mW is allowable for the dissipation across the current-sensing resistor at the full-scale current level. Although the maximum power dissipation is defined as 250 mW, a lower dissipation is preferred to improve system efficiency. Some initial assumptions are made that are used in this example: the limit setting resistor, RLIMIT, is a 1% component and the maximum tolerance specification for the internal threshold setting current source, 0.5%, is used. Given the total error budget of 5%, up to 3.5% of error is available to be attributed to the internal offset of the device.
As shown in Table 1, the maximum value calculated for the current-sensing resistor with these requirements is 2.5 mΩ. Although this value satisfies the maximum power dissipation requirement of 250 mW, headroom is available from the 5% maximum total error to reduce the value of the current-sensing resistor and reduce the power dissipation further. Selecting a 1.5-mΩ, current-sensing resistor value offers a tradeoff for reducing the power dissipation in this scenario by approximately 40%, while still remaining within the defined accuracy region.
|Maximum measurement error||5%|
|PRSENSE||Maximum allowable RSENSE power dissipation||RSENSE × IMAX 2||250||mW|
|Initial error||RLIMIT + ILIMIT tolerances||1.5%|
|RSENSE_MAX||Maximum sensing resistor value||PRSENSE / IMAX 2||2.5||mΩ|
|VSENSE_MAX||Input sense voltage||RSENSE_MAX × IMAX||25||mV|
|VOS Error||Offset voltage error||(VOS / VSENSE_MAX) × 100||2%|
|Error_Available||Maximum allowable offset error||Maximum Error – Initial Error||3.5%|
|VSENSE_MIN||Minimum input sense voltage||VOS / (Error_Available / 100)||14.3||mV|
|RSENSE_MIN||Minimum sensing resistor value||VSENSE_MIN / IMAX||1.43||mΩ|
|PRSENSE_MIN||Minimum power dissipation||RSENSE_MIN × IMAX 2||143||mW|
The device determines if an overcurrent event is present by comparing the measured differential voltage developed across the current-sensing resistor to the corresponding signal programmed at the LIMIT terminal. The threshold voltage for the LIMIT terminal can be set using a resistor or an external voltage source.
The typical approach for setting the limit threshold voltage is to connect a resistor from the LIMIT terminal to ground. The value of this resistor, RLIMIT, is chosen to create a corresponding voltage at the LIMIT terminal equivalent to the voltage, VTRIP, developed by the load current flowing through the current-sensing resistor. An internal 20-µA current source is present at the LIMIT terminal that creates the corresponding voltage depending on the value of RLIMIT. In the equations from Table 2, VTRIP represents the overcurrent threshold the device is programmed to monitor for and VLIMIT is the programmed signal set to detect the VTRIP level. The term noise adjustment factor (NAF) is included in the VLIMIT equation for the 10-µs delay setting. This value is equal to 500 µV and adjusts the operating point for the internal noise in this delay setting. The 50-µs and 100-µs delay settings do not use the NAF term in calculating the VLIMIT threshold. See Noise Adjustment Factor (NAF) for more details on the noise adjustment factor.
In Table 2, the process for calculating the required value for RLIMIT to set the appropriate threshold voltage, VLIMIT, is shown. This calculation is based on the 10-µs delay setting so the NAF term is included in the calculation. For a delay setting of 50 µs or 100 µs, the NAF term is omitted.
|VTRIP||Desired current trip value||ILOAD × RSENSE|
|VLIMIT||Programmed threshold limit voltage||VLIMIT = VTRIP|
|VLIMIT (1)||Threshold voltage||(ILIMIT × RLIMIT) – NAF|
|RLIMIT (1)||Threshold limit setting resistor||(VLIMIT + NAF) / ILIMIT|
|RLIMIT (1)||Limit setting resistor||(VLIMIT + 500 µV) / 20 µA|
TI recommends using NAF in calculating the value for VLIMIT and RLIMIT at the 10-µs delay setting. Removing NAF from the VLIMIT and RLIMIT calculation at the 10-µs delay setting lowers the trigger point of the alert output. Lowering the trigger point results in the device issuing an overcurrent alert prior to reaching the corresponding VTRIP threshold. The averaging effect included with the 50-µs and 100-µs delay settings inherently eliminates the effect internal noise has on the threshold voltage.
The second method for setting the limit voltage is to connect the LIMIT terminal to a programmable DAC (digital-to-analog converter) or other external voltage source. The benefit of this method is the ability to adjust the current limit to account for different threshold voltages that are used for different system operating conditions. For example, this method can be used in a system that has one current-limit threshold level that must be monitored during the power-up sequence but different thresholds must be monitored during other system operating modes.
In Table 3, VTRIP represents the overcurrent threshold the device is programmed to monitor for and VSOURCE is the programmed signal set to detect the VTRIP level. NAF is included in the VSOURCE equation for the 10-µs delay setting. This value equals 500 µV and is adjusts the operating point for the noise in the delay setting. The 50-µs and 100-µs delay settings do not use the NAF term in calculating the VSOURCE threshold. For these delay settings, the NAF term is omitted. See the Noise Adjustment Factor (NAF) section for more details on the noise adjustment factor.
|VTRIP||Desired current trip value||ILOAD × RSENSE|
|VSOURCE (1)||Programmed threshold limit voltage||VTRIP + NAF|
|VSOURCE (1)||Programmed signal set to detect the VTRIP level||VTRIP + 500 µV|
TI recommends using NAF in calculating the value for VSOURCE at the 10-µs delay setting. Removing NAF from the VSOURCE calculation at the 10-µs delay setting lowers the trigger point of the alert output. Lowering the trigger point results in the device issuing an overcurrent alert prior to reaching the corresponding VTRIP threshold. The averaging effect included with the 50-µs and 100-µs delay settings inherently eliminates the effect internal noise has on the threshold voltage.
The device response time for overcurrent events is adjustable based on the DELAY terminal setting. Three response time settings are available, ranging from 10 µs to 100 µs. The primary purpose for the three different delay settings is to offer a trade-off between a faster alert response and a more precise overcurrent threshold level detection.
The device has a 10-µs internal comparison window. This single comparison window is the fundamental time unit used for all three delay settings. For the 10-µs delay setting, the device compares the average of the input signal during the 10-µs comparison window to the threshold limit programmed at the LIMIT terminal. If the averaged input signal exceeds the threshold at the end of the 10-µs comparison window, the output alert triggers and pulls the ALERT terminal low. However, if the averaged input does not exceed the threshold at the end of the 10-µs comparison window, there is no change in the output alert status, which remains high to indicate that no overcurrent event is detected.
For the 50-µs delay setting, there must be five consecutive 10-µs comparison windows that result in an average input signal exceeding the threshold limit in order for the output alert to trigger and pull the ALERT terminal low. If any single 10-µs comparison window fails to detect an overcurrent condition before reaching five consecutive overcurrent comparisons, the internal counter is reset and no output alert is issued. With the internal counter reset, a new group of five consecutive 10-µs comparison windows of overcurrent conditions are required in order to trigger the alert and pull the ALERT terminal low.
The 100-µs delay setting operates in the same manner as the 50-µs method, but instead requires ten consecutive 10-µs comparison windows with an input signal exceeding the threshold limit to issue an output alert and pull the ALERT terminal low.
Requiring multiple consecutive overcurrent detections aides significantly in reducing the likelihood of system noise causing false alerts, which can be detrimental to critical system operations. However, by enabling an alert window equal to the comparison window of 10 µs, the device still has the flexibility to be used in fast overcurrent detection applications that require quick responses to rapidly changing system operating characteristics.
In Figure 22, the device alert output response is shown for a 10-µs delay setting and a 50-µs delay setting based on the same input signal condition. The initial increase of the input signal, VIN, above the VLIMIT level remains above the limit for approximately 30 µs. With the device set to the 10-µs delay setting, the overcurrent condition is detected and the alert output terminal is pulled low approximately 10 µs later. With the device set to the 50-µs delay setting, an alert is not issued because five consecutive 10-µs overcurrent measurements are not detected. With the input signal only being over the limit for 30 µs rather than the corresponding 50 µs needed for this delay setting, the device does not issue an alert under this condition. For the second instance where VIN rises above the VLIMIT threshold, the input remains above the limit for more than five consecutive 10-µs measurements, indicating an overcurrent condition and the alert output terminal is pulled low.
As discussed previously, there are three different available delay settings that are configured based on the signal connected to the DELAY terminal, as shown in Figure 23 and Table 4. The DELAY terminal must be either connected directly to ground, directly to supply, or left completely floating. Additional external resistors must not be connected to this terminal. If a resistance is required by the application to be placed in series with either the supply or ground connection to the DELAY terminal, this resistance must be limited to 1 kΩ so as to not conflict with the internal level-detection circuitry.
|DELAY||ALERT DELAY (µs)|
|Open or floating||10|
The device has a 10-µs internal comparison window where the input signal is measured to compare to the limit threshold voltage. This window continuously runs internal to the device without any external indicator or control. A comparison is made at the completion of each 10-µs comparison window to determine if the averaged input over the comparison window exceeds the limit threshold, thus indicating if an overcurrent event has occurred.
This comparison window is not synchronized with the input signal so there is an unknown timing component present. With this free-running internal timing window, an overcurrent event can occur anywhere within the 10-µs comparison window. This condition causes a variation in the amount of time before the alert appears at the output because the comparison is always made at the end of the 10-µs comparison window. Figure 24 shows the variation in time between when the input signal rises above the threshold voltage and when a change at the alert output terminal occurs.
The delay shown in Figure 24 represents the response time of the device with a 10-µs delay setting. With a
50-µs delay setting, an additional 40 µs is added to the timing response, as shown in Figure 25. A 100-µs delay setting adds 90 µs to the response time, as shown in Figure 26.
Device hysteresis is adjustable based on the setting at the hysteresis (HYS) terminal. The smallest setting for hysteresis on the device, 2 mV, is enabled by leaving the HYS terminal open and floating. A 4-mV hysteresis is set by connecting the HYS terminal to ground; connecting this terminal to the supply voltage sets the hysteresis to 8 mV, as shown in Figure 27. The HYS terminal must be either connected directly to ground, directly to supply, or left completely floating. Additional external resistors must not be connected to this terminal. If a resistance is required by the application to be placed in series with either the supply or ground connections to the HYS terminal, this resistance must be limited to 1 kΩ so as to not conflict with the internal level-detection circuitry.
The wide dynamic input range of the INA300-Q1 necessitates an adjustable hysteresis to ensure that the device can be appropriately configured based on the specific operating conditions and application requirements. Figure 28 illustrates the transition locations for the ALERT terminal based on where the input signal, VIN, is measured relative the limit threshold, VLIMIT. The corresponding hysteresis levels and physical terminal settings for the device are shown in Table 5.
The device ALERT terminal is an active-low, open-drain output. This output is designed to be pulled low when the input conditions are detected as out-of-range. This open-drain output pin is recommended to include a
10-kΩ, pull-up resistor to the supply voltage. This open-drain terminal can be pulled up to a voltage beyond the supply voltage, VS, but must not exceed 5.5 V.
The device is a high-speed, low-noise comparator that is designed to alert when the measured input signal exceeds the programmed limit level. Internal noise in the device couples into the measurement and can result in alerts being issued prior to the input signal exceeding the voltage level present at the LIMIT terminal. This known internal noise component effects the input signal measurement by causing a consistent shift in the device internal offset, resulting in a shifted trip threshold. NAF adjusts the VLIMIT setting to account for this internal shift, thus allowing for a more precise level detection of the measured current.
The NAF value is based on the noise contribution on the measurement at the 10-µs delay setting. This value is equal to 500 µV and is applied in the calculation to adjust the VLIMIT threshold level to allow for a more accurate alert trip point. The NAF term is only applied in the VLIMIT calculation at the 10-µs delay setting. The averaging effect included with the 50-µs and 100-µs delay settings inherently eliminates the effect internal noise has on the threshold voltage. The NAF term can be omitted from the RLIMIT calculation at the 10-µs delay setting with the effect of a lower trigger point of the alert output. Lowering the trigger point results in an overcurrent alert prior to reaching the corresponding VTRIP threshold.
The device has two output operating modes that are selected based on the LATCH terminal setting: transparent mode and latch mode. These modes change how the ALERT terminal responds to the changing input signal conditions.
The device is set to transparent mode when the LATCH terminal is pulled low, thus allowing the output alert state to change and follow the input signal with respect to the programmed alert threshold. For example, when the differential input signal rises above the alert threshold, the alert output terminal is pulled low. When the differential input signal drops below the alert threshold for 10 µs, the output returns to the default high output state. A common implementation using the device in transparent mode is to connect the ALERT terminal to a hardware interrupt input on a controller. As soon as an overcurrent condition is detected in the device and the ALERT terminal is pulled low, the controller interrupt terminal detects the output state change and can begin making changes to the system operation needed to address the overcurrent condition.
Some applications do not have the functionality available to continuously monitor the state of the output ALERT terminal to detect an overcurrent condition. A typical example of this application is a system that is only able to poll the ALERT terminal state periodically to determine if the system is functioning correctly. If the device is set to transparent mode in this type of application, missing the change in state of the ALERT terminal is possible when ALERT is pulled low to indicate an out-of-range event if the out-of-range condition does not appear during one of these periodic polling events.
Latch mode is specifically intended to accommodate these applications. As shown in Table 6, the device is placed in latch mode by setting the voltage on the LATCH terminal to a logic high level. The difference between latch mode and transparent mode is how the alert output responds when an overcurrent event ends. In transparent mode, when the differential input signal drops below the limit threshold level for 10 µs, the output state returns to the default high setting to indicate that the overcurrent event had ended.
In latch mode, when an overlimit condition is detected and the ALERT terminal is pulled low, the ALERT terminal does not return to the default high level when the differential input signal drops below the alert threshold level for 10 µs. To clear the alert the LATCH terminal must be pulled low for at least 20 µs. Pulling the LATCH terminal low allows the ALERT terminal to return to the default high level, provided that the differential input signal has dropped below the alert threshold. If the input signal is still above the threshold limit when the LATCH terminal is pulled low, the ALERT terminal remains low. When the alert condition is detected by the system controller (the LATCH terminal) can be set back to high in order to place the device back in latch mode.
|OUTPUT MODE||LATCH TERMINAL SETTING|
|Transparent mode||LATCH = low|
|Latch mode||LATCH = high|
The latch and transparent modes are represented in Figure 29. In Figure 29 when VIN drops back below the VLIMIT threshold for the first time, the LATCH terminal is pulled high. With the LATCH terminal pulled high, the device is set to latch mode so that the alert output state does not return high when the input signal drops below the VLIMIT threshold. Only when the LATCH terminal is pulled low does the ALERT terminal return to the default high level, indicating that the input signal is below the limit threshold. When the input signal drops below the limit threshold for the second time, the LATCH terminal is already pulled low. The device is set to transparent mode at this point and the ALERT terminal is pulled back high when the input signal drops below the alert threshold.
The INA300-Q1 device has an ENABLE terminal that allows the device to be placed into an active enabled state or a low-power disabled state where less than 10 µA is consumed from all terminals. This disable state allows the device to be used in applications where low current consumption is required to extend battery life where constant monitoring is not required. The INA300-Q1 device requires approximately 20 µs to enter the low-power state when the ENABLE terminal transitions from high to low, as shown in Table 7. To return to the enabled active state, the INA300-Q1 device requires approximately 300 µs to return to normal operation when the ENABLE terminal transitions from low to high, taking the device out of the low-power state.
|ENABLE MODE||ENABLE TERMINAL SETTING|
|Disable mode||ENABLE = low|
|Enable mode||ENABLE = high|
The internal counter that determines if the necessary consecutive 10-µs window comparison alert conditions are reached for the 50-µs and 100-µs delay setting is reset when the device is put into a disabled state. When the device is re-enabled, the counter restarts.
External system noise can have a significant effect in the ability of a comparator to accurately measure and detect whether input signals exceed the reference threshold levels, indicating an overrange condition. The device is susceptible to external noise, although the 50-µs and 100-µs delay settings are can mitigate the impact of noise based on the effective averaging achieved in these modes. The obvious effect that external noise can have on the operation of a comparator is to cause a false alert condition. If a comparator detects a large noise transient coupled into the signal, the device can interpret this transient as an overrange condition.
External filtering can help reduce the amount of noise that reaches the comparator inputs, and can reduce the likelihood of a false alert from occurring. The tradeoff to adding this noise filter is increased comparator response time, because of the input signal being filtered as well as the noise. Figure 30 shows the implementation of an input filter for the device.
Limiting the amount of input resistance used in this filter is important because this resistance can have a significant effect on the input signal that reaches the device input pins resulting from the device input bias currents. A typical system implementation involves placing the current-sensing resistor near the device so the traces are short and the trace impedance is small. This layout helps reduce the ability of coupling additional noise into the measurement. Under these conditions, the characteristics of the input bias currents have minimal effect on device performance.
As shown in Figure 31, the input bias currents increase in opposite directions when the differential input voltage increases. This increase results from the design of the device, which allows common-mode input voltages to far exceed the device supply voltage range. With input filter resistors now placed in series with these unequal input bias currents, there are unequal voltage drops developed across the input resistors. The difference between the two drops appears as an added signal that (in this case) subtracts from the voltage developed across the current-sensing resistor, reducing the signal that reaches the device input terminals. Smaller value input resistors reduce this effect of signal attenuation to allow for a more accurate measurement.
For example, with a differential voltage of 10 mV developed across a current-sensing resistor and using 100-Ω resistors, the differential signal that reaches the device is 9.8 mV. A measurement error of 2% is created as a result of the external input filter resistors. Using 10-Ω input filter resistors instead of the 100-Ω resistors reduces this added error from 2% to 0.2%.
With a small amount of additional circuitry, the device can be used in circuits subject to transients higher than
36 V. Use only zener diodes or zener-type transient absorbers (sometimes referred to as Transzorbs). Any other type of transient absorber has an unacceptable time delay. Start by adding a pair of resistors, as shown in Figure 32, as a working impedance for the zener diode. Keeping these resistors as small as possible is best, preferably 100 Ω or less. Larger values can be used with an additional error induced resulting from a reduced signal that reaches the device input terminals. Because this circuit limits only short-term transients, many applications are satisfied with a 100-Ω resistor along with conventional zener diodes of the lowest power rating available. This combination uses the least amount of board space. These diodes can be found in SOT-523 or SOD-523 packages.