ZHCSGK5A July   2017  – July 2017 ESD401

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings — JEDEC Specification 
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-4 EFT Protection
      3. 7.3.3 IEC 61000-4-5 Surge Protection
      4. 7.3.4 IO Capacitance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Low Leakage Current
      7. 7.3.7 Low ESD Clamping Voltage
      8. 7.3.8 Industrial Temperature Range
      9. 7.3.9 Industry Standard Footprint
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The ESD401 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.

Typical Application

ESD401 SLVSE49_app_diagram.gif Figure 12. USB 2.0 ESD Schematic

Design Requirements

For this design example, two ESD401 devices are being used in a USB 2.0 application. This provides a complete ESD protection scheme.

Given the USB 2.0 application, the parameters listed in Table 1 are known.

Table 1. Design Parameters

DESIGN PARAMETER VALUE
Signal range on DP-DM lines 0 V to 3.6 V
Operating frequency on DP-DM lines up to 240 MHz or 480 Mbps

Detailed Design Procedure

Signal Range

The ESD401 supports signal ranges between –5.5 V and 5.5 V, which supports the USB 2.0 signal range of 0 to 3.6 V on the DM/DP lines..

Operating Frequency

The ESD401 has a 0.85 pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps.

Application Curves

ESD401 D009_SLVSE49.gif Figure 13. Insertion Loss
ESD401 3Gbps_nodevice.gif Figure 14. Eye Diagram - 3-Gbps Signal No Device
ESD401 3Gbps_device.gif Figure 15. Eye Diagram - 3-Gbps Signal With ESD401