ZHCSGT3C August   2017  – January 2023 DS90UB954-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics CSI-2
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  RX MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Crystal Recommendations
      6. 7.4.6  Receiver Port Control
        1. 7.4.6.1 Video Stream Forwarding
      7. 7.4.7  LOCK and PASS Status
      8. 7.4.8  Input Jitter Tolerance
      9. 7.4.9  Adaptive Equalizer
        1. 7.4.9.1 Adaptive Equalizer Algorithm
        2. 7.4.9.2 AEQ Settings
          1. 7.4.9.2.1 AEQ Start-Up and Initialization
          2. 7.4.9.2.2 AEQ Range
          3. 7.4.9.2.3 AEQ Timing
          4. 7.4.9.2.4 AEQ Threshold
      10. 7.4.10 Channel Monitor Loop-Through Output Driver (CMLOUT)
        1. 7.4.10.1 Code Example for CMLOUT FPD-Link III RX Port 0:
      11. 7.4.11 RX Port Status
        1. 7.4.11.1 RX Parity Status
        2. 7.4.11.2 FPD-Link Decoder Status
        3. 7.4.11.3 RX Port Input Signal Detection
        4. 7.4.11.4 Line Counter
        5. 7.4.11.5 Line Length
      12. 7.4.12 Sensor Status
      13. 7.4.13 GPIO Support
        1. 7.4.13.1 GPIO Input Control and Status
        2. 7.4.13.2 GPIO Output Pin Control
        3. 7.4.13.3 51
        4. 7.4.13.4 Forward Channel GPIO
        5. 7.4.13.5 Back Channel GPIO
        6. 7.4.13.6 Other GPIO Pin Controls
      14. 7.4.14 Line Valid and Frame Valid Indicators
      15. 7.4.15 CSI-2 Protocol Layer
      16. 7.4.16 CSI-2 Short Packet
      17. 7.4.17 CSI-2 Long Packet
      18. 7.4.18 CSI-2 Data Type Identifier
      19. 7.4.19 Virtual Channel and Context
      20. 7.4.20 CSI-2 Input Mode Virtual Channel Mapping
        1. 7.4.20.1 Example 1
        2. 7.4.20.2 Example 2:
      21. 7.4.21 CSI-2 Transmitter Frequency
      22. 7.4.22 CSI-2 Replicate Mode
      23. 7.4.23 CSI-2 Transmitter Output Control
      24. 7.4.24 CSI-2 Transmitter Status
      25. 7.4.25 Video Buffers
      26. 7.4.26 CSI-2 Line Count and Line Length
      27. 7.4.27 FrameSync Operation
        1. 7.4.27.1 External FrameSync Control
        2. 7.4.27.2 Internally Generated FrameSync
          1. 7.4.27.2.1 Code Example for Internally Generated FrameSync
      28. 7.4.28 CSI-2 Forwarding
        1. 7.4.28.1 Enabling and Disabling the CSI-2 Transmitter
        2. 7.4.28.2 Best-Effort Round Robin CSI-2 Forwarding
        3. 7.4.28.3 Synchronized Forwarding
        4. 7.4.28.4 Basic Synchronized Forwarding
          1. 7.4.28.4.1 Code Example for Basic Synchronized Forwarding
        5. 7.4.28.5 Line-Interleave Forwarding
          1. 7.4.28.5.1 Code Example for Line-Interleave Forwarding
        6. 7.4.28.6 Line-Concatenated Forwarding
          1. 7.4.28.6.1 Code Example for Line-Concatenate Forwarding
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus and Bidirectional Control Channel
        1. 7.5.1.1 Bidirectional Control
        2. 7.5.1.2 Device Address
        3. 7.5.1.3 Basic I2C Serial Bus Operation
      2. 7.5.2  I2C Target Operation
      3. 7.5.3  Remote Target Operation
        1. 7.5.3.1 Remote I2C Targets Data Throughput
      4. 7.5.4  Remote Target Addressing
      5. 7.5.5  Broadcast Write to Remote Target Devices
        1. 7.5.5.1 Code Example for Broadcast Write
      6. 7.5.6  I2C Controller Proxy
      7. 7.5.7  I2C Controller Proxy Timing
        1. 7.5.7.1 Code Example for Configuring Fast Mode Plus I2C Operation
      8. 7.5.8  Interrupt Support
        1. 7.5.8.1 Code Example to Enable Interrupts
        2. 7.5.8.2 FPD-Link III Receive Port Interrupts
          1. 7.5.8.2.1 Interrupts on Forward Channel GPIO
          2. 7.5.8.2.2 Interrupts on Change in Sensor Status
        3. 7.5.8.3 Code Example to Readback Interrupts
        4. 7.5.8.4 CSI-2 Transmit Port Interrupts
      9. 7.5.9  Error Handling
        1. 7.5.9.1 Receive Frame Threshold
        2. 7.5.9.2 Port PASS Control
      10. 7.5.10 Timestamp – Video Skew Detection
      11. 7.5.11 Pattern Generation
        1. 7.5.11.1 Reference Color Bar Pattern
        2. 7.5.11.2 Fixed Color Patterns
        3. 7.5.11.3 Packet Generator Programming
          1. 7.5.11.3.1 Determining Color Bar Size
        4. 7.5.11.4 Code Example for Pattern Generator
      12. 7.5.12 FPD-Link BIST Mode
        1. 7.5.12.1 BIST Operation Through BISTEN Pin
        2. 7.5.12.2 BIST Operation Through Register Control
    6. 7.6 Register Maps
      1. 7.6.1   I2C Device ID Register
      2. 7.6.2   Reset Register
      3. 7.6.3   General Configuration Register
      4. 7.6.4   Revision/Mask ID Register
      5. 7.6.5   DEVICE_STS Register
      6. 7.6.6   PAR_ERR_THOLD_HI Register
      7. 7.6.7   PAR_ERR_THOLD_LO Register
      8. 7.6.8   BCC Watchdog Control Register
      9. 7.6.9   I2C Control 1 Register
      10. 7.6.10  I2C Control 2 Register
      11. 7.6.11  SCL High Time Register
      12. 7.6.12  SCL Low Time Register
      13. 7.6.13  RX_PORT_CTL Register
      14. 7.6.14  IO_CTL Register
      15. 7.6.15  GPIO_PIN_STS Register
      16. 7.6.16  GPIO_INPUT_CTL Register
      17. 7.6.17  GPIO0_PIN_CTL Register
      18. 7.6.18  GPIO1_PIN_CTL Register
      19. 7.6.19  GPIO2_PIN_CTL Register
      20. 7.6.20  GPIO3_PIN_CTL Register
      21. 7.6.21  GPIO4_PIN_CTL Register
      22. 7.6.22  GPIO5_PIN_CTL Register
      23. 7.6.23  GPIO6_PIN_CTL Register
      24. 7.6.24  RESERVED Register
      25. 7.6.25  FS_CTL Register
      26. 7.6.26  FS_HIGH_TIME_1 Register
      27. 7.6.27  FS_HIGH_TIME_0 Register
      28. 7.6.28  FS_LOW_TIME_1 Register
      29. 7.6.29  FS_LOW_TIME_0 Register
      30. 7.6.30  MAX_FRM_HI Register
      31. 7.6.31  MAX_FRM_LO Register
      32. 7.6.32  CSI_PLL_CTL Register
      33. 7.6.33  FWD_CTL1 Register
      34. 7.6.34  FWD_CTL2 Register
      35. 7.6.35  FWD_STS Register
      36. 7.6.36  INTERRUPT_CTL Register
      37. 7.6.37  INTERRUPT_STS Register
      38. 7.6.38  TS_CONFIG Register
      39. 7.6.39  TS_CONTROL Register
      40. 7.6.40  TS_LINE_HI Register
      41. 7.6.41  TS_LINE_LO Register
      42. 7.6.42  TS_STATUS Register
      43. 7.6.43  TIMESTAMP_P0_HI Register
      44. 7.6.44  TIMESTAMP_P0_LO Register
      45. 7.6.45  TIMESTAMP_P1_HI Register
      46. 7.6.46  TIMESTAMP_P1_LO Register
      47. 7.6.47  RESERVED Register
      48. 7.6.48  CSI_CTL Register
      49. 7.6.49  CSI_CTL2 Register
      50. 7.6.50  CSI_STS Register
      51. 7.6.51  CSI_TX_ICR Register
      52. 7.6.52  CSI_TX_ISR Register
      53. 7.6.53  CSI_TEST_CTL Register
      54. 7.6.54  CSI_TEST_PATT_HI Register
      55. 7.6.55  CSI_TEST_PATT_LO Register
      56. 7.6.56  RESERVED Register
      57. 7.6.57  RESERVED Register
      58. 7.6.58  RESERVED Register
      59. 7.6.59  RESERVED Register
      60. 7.6.60  RESERVED Register
      61. 7.6.61  RESERVED Register
      62. 7.6.62  SFILTER_CFG Register
      63. 7.6.63  AEQ_CTL1 Register
      64. 7.6.64  AEQ_ERR_THOLD Register
      65. 7.6.65  RESERVED Register
      66. 7.6.66  FPD3_CAP Register
      67. 7.6.67  RAW_EMBED_DTYPE Register
      68. 7.6.68  FPD3_PORT_SEL Register
      69. 7.6.69  RX_PORT_STS1 Register
      70. 7.6.70  RX_PORT_STS2 Register
      71. 7.6.71  RX_FREQ_HIGH Register
      72. 7.6.72  RX_FREQ_LOW Register
      73. 7.6.73  SENSOR_STS_0 Register
      74. 7.6.74  SENSOR_STS_1 Register
      75. 7.6.75  SENSOR_STS_2 Register
      76. 7.6.76  SENSOR_STS_3 Register
      77. 7.6.77  RX_PAR_ERR_HI Register
      78. 7.6.78  RX_PAR_ERR_LO Register
      79. 7.6.79  BIST_ERR_COUNT Register
      80. 7.6.80  BCC_CONFIG Register
      81. 7.6.81  DATAPATH_CTL1 Register
      82. 7.6.82  DATAPATH_CTL2 Register
      83. 7.6.83  SER_ID Register
      84. 7.6.84  SER_ALIAS_ID Register
      85. 7.6.85  TargetID[0] Register
      86. 7.6.86  TargetID[1] Register
      87. 7.6.87  TargetID[2] Register
      88. 7.6.88  TargetID[3] Register
      89. 7.6.89  TargetID[4] Register
      90. 7.6.90  TargetID[5] Register
      91. 7.6.91  TargetID[6] Register
      92. 7.6.92  TargetID[7] Register
      93. 7.6.93  TargetAlias[0] Register
      94. 7.6.94  TargetAlias[1] Register
      95. 7.6.95  TargetAlias[2] Register
      96. 7.6.96  TargetAlias[3] Register
      97. 7.6.97  TargetAlias[4] Register
      98. 7.6.98  TargetAlias[5] Register
      99. 7.6.99  TargetAlias[6] Register
      100. 7.6.100 TargetAlias[7] Register
      101. 7.6.101 PORT_CONFIG Register
      102. 7.6.102 BC_GPIO_CTL0 Register
      103. 7.6.103 BC_GPIO_CTL1 Register
      104. 7.6.104 RAW10_ID Register
      105. 7.6.105 RAW12_ID Register
      106. 7.6.106 CSI_VC_MAP Register
      107. 7.6.107 LINE_COUNT_HI Register
      108. 7.6.108 LINE_COUNT_LO Register
      109. 7.6.109 LINE_LEN_1 Register
      110. 7.6.110 LINE_LEN_0 Register
      111. 7.6.111 FREQ_DET_CTL Register
      112. 7.6.112 MAILBOX_1 Register
      113. 7.6.113 MAILBOX_2 Register
      114. 7.6.114 CSI_RX_STS Register
      115. 7.6.115 CSI_ERR_COUNTER Register
      116. 7.6.116 PORT_CONFIG2 Register
      117. 7.6.117 PORT_PASS_CTL Register
      118. 7.6.118 SEN_INT_RISE_CTL Register
      119. 7.6.119 SEN_INT_FALL_CTL Register
      120. 7.6.120 RESERVED Register
      121. 7.6.121 REFCLK_FREQ Register
      122. 7.6.122 RESERVED Register
      123. 7.6.123 IND_ACC_CTL Register
      124. 7.6.124 IND_ACC_ADDR Register
      125. 7.6.125 IND_ACC_DATA Register
      126. 7.6.126 BIST Control Register
      127. 7.6.127 RESERVED Register
      128. 7.6.128 RESERVED Register
      129. 7.6.129 RESERVED Register
      130. 7.6.130 RESERVED Register
      131. 7.6.131 MODE_IDX_STS Register
      132. 7.6.132 LINK_ERROR_COUNT Register
      133. 7.6.133 FPD3_ENC_CTL Register
      134. 7.6.134 RESERVED Register
      135. 7.6.135 FV_MIN_TIME Register
      136. 7.6.136 RESERVED Register
      137. 7.6.137 GPIO_PD_CTL Register
      138. 7.6.138 RESERVED Register
      139. 7.6.139 PORT_DEBUG Register
      140. 7.6.140 RESERVED Register
      141. 7.6.141 AEQ_CTL2 Register
      142. 7.6.142 AEQ_STATUS Register
      143. 7.6.143 ADAPTIVE EQ BYPASS Register
      144. 7.6.144 AEQ_MIN_MAX Register
      145. 7.6.145 RESERVED Register
      146. 7.6.146 RESERVED Register
      147. 7.6.147 PORT_ICR_HI Register
      148. 7.6.148 PORT_ICR_LO Register
      149. 7.6.149 PORT_ISR_HI Register
      150. 7.6.150 PORT_ISR_LO Register
      151. 7.6.151 FC_GPIO_STS Register
      152. 7.6.152 FC_GPIO_ICR Register
      153. 7.6.153 SEN_INT_RISE_STS Register
      154. 7.6.154 SEN_INT_FALL_STS Register
      155. 7.6.155 FPD3_RX_ID0 Register
      156. 7.6.156 FPD3_RX_ID1 Register
      157. 7.6.157 FPD3_RX_ID2 Register
      158. 7.6.158 FPD3_RX_ID3 Register
      159. 7.6.159 FPD3_RX_ID4 Register
      160. 7.6.160 FPD3_RX_ID5 Register
      161. 7.6.161 I2C_RX0_ID Register
      162. 7.6.162 I2C_RX1_ID Register
      163. 7.6.163 RESERVED Register
      164. 7.6.164 RESERVED Register
      165. 7.6.165 Indirect Access Registers
      166. 7.6.166 284
      167. 7.6.167 Reserved Register
      168. 7.6.168 PGEN_CTL Register
      169. 7.6.169 PGEN_CFG Register
      170. 7.6.170 PGEN_CSI_DI Register
      171. 7.6.171 PGEN_LINE_SIZE1 Register
      172. 7.6.172 PGEN_LINE_SIZE0 Register
      173. 7.6.173 PGEN_BAR_SIZE1 Register
      174. 7.6.174 PGEN_BAR_SIZE0 Register
      175. 7.6.175 PGEN_ACT_LPF1 Register
      176. 7.6.176 PGEN_ACT_LPF0 Register
      177. 7.6.177 PGEN_TOT_LPF1 Register
      178. 7.6.178 PGEN_TOT_LPF0 Register
      179. 7.6.179 PGEN_LINE_PD1 Register
      180. 7.6.180 PGEN_LINE_PD0 Register
      181. 7.6.181 PGEN_VBP Register
      182. 7.6.182 PGEN_VFP Register
      183. 7.6.183 PGEN_COLOR0 Register
      184. 7.6.184 PGEN_COLOR1 Register
      185. 7.6.185 PGEN_COLOR2 Register
      186. 7.6.186 PGEN_COLOR3 Register
      187. 7.6.187 PGEN_COLOR4 Register
      188. 7.6.188 PGEN_COLOR5 Register
      189. 7.6.189 PGEN_COLOR6 Register
      190. 7.6.190 PGEN_COLOR7 Register
      191. 7.6.191 PGEN_COLOR8 Register
      192. 7.6.192 PGEN_COLOR9 Register
      193. 7.6.193 PGEN_COLOR10 Register
      194. 7.6.194 PGEN_COLOR11 Register
      195. 7.6.195 PGEN_COLOR12 Register
      196. 7.6.196 PGEN_COLOR13 Register
      197. 7.6.197 PGEN_COLOR14 Register
      198. 7.6.198 RESERVED Register
      199. 7.6.199 CSI0_TCK_PREP Register
      200. 7.6.200 CSI0_TCK_ZERO Register
      201. 7.6.201 CSI0_TCK_TRAIL Register
      202. 7.6.202 CSI0_TCK_POST Register
      203. 7.6.203 CSI0_THS_PREP Register
      204. 7.6.204 CSI0_THS_ZERO Register
      205. 7.6.205 CSI0_THS_TRAIL Register
      206. 7.6.206 CSI0_THS_EXIT Register
      207. 7.6.207 CSI0_TPLX Register
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 System
      2. 8.1.2 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. Power Supply Recommendations
    1. 9.1 VDD and VDDIO Power Supply
    2. 9.2 Power-Up Sequencing
      1. 9.2.1 PDB Pin
      2. 9.2.2 System Initialization
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
      1. 10.1.1 Ground
      2. 10.1.2 Routing FPD-Link III Signal Traces and PoC Filter
      3. 10.1.3 Routing CSI-2 Signal Traces
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Tape and Reel Information

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Revision History

Changes from Revision B (December 2018) to Revision C (January 2023)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将所有旧术语实例更改为控制器和目标Go
  • Revised the PDB pin voltage for normal operationGo
  • Changed the VDD11 pin descriptions for clarityGo
  • Added a link to Design Requirements under the RIN pinsGo
  • Updated the VIH and VIL specifications of pins PDB, XIN/REFCLK, and VDD_SELGo
  • Removed the mention of CSI-2 non-synchronous clocking modeGo
  • Changed the bits that need to be modified for Clock Mode Go
  • Changed the names of registers CAM_INT_RISE_STS and CAM_INT_FALL_STS to SEN_INT_RISE_STS and SEN_INT_FALL_STS.Go
  • Removed the mention of setting the REF_CLK_MODE bit as it is a reserved bitGo
  • Fixed typos in the internal FrameSync calculationsGo
  • Rewrote the basic synchronized forwarding code example to set both sensors to use CSI-2 serializersGo
  • Added in that VVDDIO must match VI2C Go
  • Removed the mention of 'PDB' from register 0x0DGo
  • Changed BCC_Config Register[2:0] binary setting value 0b111 to reserved.Go
  • Changed PORT_CONFIG2[5] default value to 0x1Go
  • Changed suggested ferrite beads for 4G FPD-Link PoC Network from 1500 kΩ to 1.5 kΩ Go
  • Changed PoC network impedance recommendation from 2kΩ to 1kΩGo
  • Updated the PoC descriptionGo
  • Removed the insertion and return loss values from the table on Suggested Characteristics for Single-Ended PCB Traces With Attached PoC NetworksGo
  • Added a note to explain the differences between the decoupling capacitorsGo
  • Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo
  • Changed the value of the capacitor for pin VDD11_CSI from 1-μF to 10-μF in the diagram where VDD_SEL = HIGHGo
  • Moved the additional notes in the typical application diagram from the picture to below the diagramGo
  • Added a note to clarify the power-up sequence between VDD18 and VDDIOGo
  • Removed T0 and T2 from power-up sequenceGo
  • Added a note to clarify that a hard reset is optional in the power-up sequenceGo
  • Added in T7, the PDB to I2C ready delay, to the power-up sequenceGo
  • Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo

Changes from Revision A (September 2018) to Revision B (December 2018)

  • Changed the intended content bandwidth limit from 2.528 Gbps to 3.328 Gbps Go

Changes from Revision * (August 2017) to Revision A (September 2018)

  • Changed supply voltage test condition from V(VDD11)(VDD_SEL = LOW ONLY to V(VDD11)(VDD_SEL = HIGH ONLY) Go
  • Added spread-spectrum reference clock modulation percentage parameter to the ROC tablesGo
  • Added V(VDDIO) VDD18 ±50mV test condition to the high level output voltage parameterGo
  • Added V(VDDIO) = VDD18 ±50mV test to the low level output voltage parameterGo
  • Added PDB pin/frequency test condition and values to the high level input voltage parameterGo
  • Added PDB pin/frequency test condition and values to the low level input voltage parameter Go
  • Changed output short circuit current symbol from Isc to IosGo
  • Added AEQ rating ±3ms RAW mode to the deserializer data lock time parameterGo
  • Added data bit rate minimum and typical values to the REFCLK = 23 MHz and REFCLK = 26 MHz test conditionsGo
  • Added DDR clock frequency minmum and typical values to the REFCLK = 23 MHz and REFCLK = 26 MHz test conditionsGo
  • Added the text '1.5 Gbps' after the 'Data rate <' and 'Data rate >' text in slew rate test conditions for falling and rising edgeGo
  • Changed the UI instantaneous maximum value from 12.5 ns to 2.7 nsGo
  • Added discrete synch signals requirement when using DVP format Go
  • Changed FPD3_PCLK to fPCLK in the RAW mode line rate calculations Go
  • Added information about YUV support Go
  • Removed Coax/STP column and reorganized rows. Go
  • Relaxed REFCLK Oscillator jitter specification to 200 ps maximum Go
  • Relaxed REFCLK Oscillator rise and fall time to 6 ns maximum Go
  • Added REFCLK spread-spectrum modulation percentage and frequency Go
  • Changed Text from: AEQ_FLOOR value to: ADAPTIVE_EQ_FLOOR_VALUE Go
  • Updated Forward Channel GPIO typical latency valueGo
  • Updated Back Channel GPIO typical latency and jitter for 50 Mbps rateGo
  • Added need for discrete synch signals in DVP mode and included RAW/YUV supportGo
  • Changed from GPIO7 pin to GPIO6 pinGo
  • Changed Text from: The total period of the FrameSync is (1 s / 60 hz) / 600 ns to: The total period of the FrameSync is (1 / 60 hz) / 600 nsGo
  • Deleted Sentence "It is recommended to forward the relevant RX port data streams prior to enabling the CSI-2 TX output"Go
  • Added Enabling and Disabling the CSI-2 Transmitter section Go
  • Changed Sensor A and B to Sensor X in definition listGo
  • Changed Node VDDIO to VI2C for SCL and SDA signal lines Go
  • Changed Register 0x7C to register 0x7DGo
  • Changed BIST_CTL to BIST Control to match register mapGo
  • Changed Parity Error Threshold High to PAR_ERR_THOLD_HIGo
  • Changed Parity Error Threshold Low to PAR_ERR_THOLD_LOGo
  • Added Cross-reference to GPIO4_OUT_SRC bit descriptionGo
  • Changed GPIO5_OUT_VAL bit description text from: GPIO5_OUT_SEL[2:0] = 00 to: GPIO5_OUT_SEL[2:0] = 000Go
  • Changed GPIO6_OUT_VAL bit description text from: GPIO6_OUT_SEL[2:0] = 00 to: GPIO6_OUT_SEL[2:0] = 000Go
  • Changed FS_GEN_MODE bit description text from: 'FS_HIGH_TIME and FS_LOW_TIME register values' to: 'FS_HIGH_TIME [15:0] and FS_LOW_TIME [15:0] register values' for clarityGo
  • Changed INT bit to INTERRUPT_STS bit in INTERRUPT_STS bit descriptionGo
  • Changed RESERVED bit numbers from: 6:4 to: 6:5Go
  • Changed RESERVED bit description text from: CSI_PLL to: CSI_PLL_CTL Go
  • Added sentence about RX port specific register for registers 0x4A, 0x4B, 0x4D - 0x7F, 0xD0 - 0xDF Go
  • Updated RX_PORT_STS2 register bit 1 field and description Go
  • Changed VOLT1_SENSE_LEVEL to VOLT0_SENSE_LEVELGo
  • Changed PAR_ERROR line _BYTE_1 to PAR_ERROR _BYTE_1 and RX PARITY CHECKER ENABLE to RX_PARITY_CHECKER_ENABLEGo
  • Changed RX PARITY CHECKER ENABLE to RX_PARITY_CHECKER_ENABLEGo
  • Changed BCC_Config Register 0x58[2:0] binary setting value from 0b100 to 0b010 to select 10 Mbps non-synchronous back channel rate.Go
  • Removed Text 'This field is normally loaded from the remote serializer. It can be overwritten if the OVERRIDE_FC_CONFIG bit in the DATAPATH_CTL0 register is 1.' from the RESERVED bit descriptionGo
  • Changed PASSPARITY-ERR to PASS_PARITY_ERRGo
  • Removed Broken link in the IND_ACC_CTL register tableGo
  • Changed IA_SEL bit enumerations from: 0001-0100 and 1000-0111 to: 00011–0100 and 1000–1111Go
  • Changed RESERVED Register to FPD3_ENC_CTL Go
  • Changed RESERVED bit numbers from: 5:3 to: 4:2 Go
  • Changed ADAPTIVE_EQ_FLOOR_VALUE bit description from: register {reg_35[5:4]} to: register 0xD2[2]Go
  • Changed IE_FC_SENS_STS bit description from: Camera and CAM to: Sensor and SENGo
  • Fixed Broken link in Power Over Coax sectionGo
  • Redraw the PoC Network diagram Go
  • Updated Return Loss S11 values Go
  • Redraw RINx STP setting for figure "Typical Connection Diagram STP With External 1.1-V supply"Go
  • Fixed Broken links in the Detailed Design Procedure sectionGo
  • Removed Second paragraph in System Examples Go