SNLS338F January   2011  – November 2014 DS100BR111

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Electrical Characteristics — Serial Management Bus Interface
    6. 7.6 Timing Requirements — LOS and ENABLE / DISABLE Timing
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Control Pin Settings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Slave Mode
      3. 8.4.3 SMBus Master Mode
      4. 8.4.4 Signal Conditioning Settings
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer Of Data Via the SMBus
      3. 8.5.3 SMBus Transactions
      4. 8.5.4 Writing a Register
      5. 8.5.5 Reading a Register
      6. 8.5.6 EEPROM Programming
        1. 8.5.6.1 Master EEPROM Programming
        2. 8.5.6.2 EEPROM Address Mapping
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity in 10G-KR Applications
      2. 9.1.2 OOB (Out-of-Band) Functionality in SAS/SATA Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
        1. 9.2.3.1 Equalization Results (Pre-Channel Only)
        2. 9.2.3.2 Equalization and De-Emphasis Results (Pre-channel and Post-channel, No Tx Source De-emphasis)
        3. 9.2.3.3 Equalization and De-Emphasis Results (Pre-channel and Post-channel, -6 dB Tx Source De-emphasis)
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Bypass
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

1 Features

  • Two Channel Repeaters for up to 10.3 Gbps
    • DS100BR210 : 2x Unidirectional Channels
    • DS100BR111 : 1x Bidirectional Lane
  • 10G-KR Bi-directional Interface Compatibility
    • Allows for Back-channel Communication and Training
  • Low 65 mW/channel (Typical) Power Consumption, with Option to Power Down Unused Channels
  • Advanced Signal Conditioning Features
    • Receive Equalization up to +36 dB
    • Transmit De-emphasis up to -12 dB
    • Transmit VOD Control: 700 to 1300 mVp-p
    • Low Residual DJ at 10.3 Gbps
  • Programmable Via Pin Selection, EEPROM, or SMBus Interface
  • Single Supply Voltage: 2.5 V or 3.3 V
  • Flow-thru Pinout in 4 mm × 4 mm 24-pin Leadless WQFN Package
  • 5 kV HBM ESD Rating
  • -40 to 85°C Operating Temperature Range

2 Applications

  • High-speed Active Copper Cable Modules and FR-4 Backplane in Communication Systems
  • 10GE, 10G-KR, FC, SAS, SATA 3/6 Gbps (with OOB Detection), InfiniBand, CPRI, RXAUI and many others

3 Description

The DS100BR111 is an extremely low power, high performance repeater designed to support serial links with data rates up to 10.3 Gbps. The DS100BR111 pinout is configured as one bidirectional lane (one transmit, one receive channel). The DS100BR111 inputs feature a powerful 4-stage continuous time linear equalizer (CTLE) to provide a boost of up to +36 dB at 5 GHz and open an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect mediums such as board traces or twin-axial copper cables. The transmitter features a programmable output de-emphasis driver with up to -12 dB and can drive output voltage levels from 700 mVp-p to 1300 mVp-p.

When configured as a 10G-KR repeater, the DS100BR111 allows the KR host and the end point to optimize the full link by adjusting transmit and receive equalizer coefficients using back-channel communication techniques specified by the 802.3ap Ethernet standard.

The programmable settings can be applied via pin control, SMBus protocol, or an external EEPROM. In the EEPROM mode, the configuration information is automatically loaded on power up, thereby eliminating the need for an external microprocessor or software driver.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS100BR111 WQFN (24) 4.00 mm x 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

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Typical Application

app_diagram.gif