SLVSET1 August   2018 DRV8873

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
        1. 7.3.1.1 Control Modes
        2. 7.3.1.2 Half-Bridge Operation
        3. 7.3.1.3 Internal Current Sense and Current Regulation
        4. 7.3.1.4 Slew-Rate Control
        5. 7.3.1.5 Dead Time
        6. 7.3.1.6 Propagation Delay
        7. 7.3.1.7 nFAULT Pin
        8. 7.3.1.8 nSLEEP as SDO Reference
      2. 7.3.2 Motor Driver Protection Circuits
        1. 7.3.2.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.2.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.2.3 Overcurrent Protection (OCP)
          1. 7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
          3. 7.3.2.3.3 Report Only (OCP_MODE = 10b)
          4. 7.3.2.3.4 Disabled (OCP_MODE = 11b)
        4. 7.3.2.4 Open-Load Detection (OLD)
          1. 7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
          2. 7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
        5. 7.3.2.5 Thermal Shutdown (TSD)
          1. 7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
          2. 7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
        6. 7.3.2.6 Thermal Warning (OTW)
      3. 7.3.3 Hardware Interface
        1. 7.3.3.1 MODE (Tri-Level Input)
        2. 7.3.3.2 Slew Rate
    4. 7.4 Device Functional Modes
      1. 7.4.1 Motor Driver Functional Modes
        1. 7.4.1.1 Sleep Mode (nSLEEP = 0)
        2. 7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
        3. 7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
        4. 7.4.1.4 nSLEEP Reset Pulse
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Status Registers
        1. 7.6.1.1 FAULT Status Register Name (address = 0x00)
          1. Table 21. FAULT Status Register Field Descriptions
        2. 7.6.1.2 DIAG Status Register Name (address = 0x01)
          1. Table 22. DIAG Status Register Field Descriptions
      2. 7.6.2 Control Registers
        1. 7.6.2.1 IC1 Control Register (address = 0x02)
          1. Table 24. IC1 Control Register Field Descriptions
        2. 7.6.2.2 IC2 Control Register (address = 0x03)
          1. Table 25. IC2 Control Register Field Descriptions
        3. 7.6.2.3 IC3 Control Register (address = 0x04)
          1. Table 26. IC3 Control Register Field Descriptions
        4. 7.6.2.4 IC4 Control Register (address = 0x05)
          1. Table 27. IC4 Control Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Motor Voltage
        2. 8.2.1.2 Drive Current and Power Dissipation
        3. 8.2.1.3 Sense Resistor
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Considerations
        2. 8.2.2.2 Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

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6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
VVM VM operating voltage 4.5 38 V
IVM VM operating supply current VVM = 13.5 V; nSLEEP = 1; DISABLE =0 5 10 mA
IVM(Q) VM sleep mode supply current VVM = 13.5 V; nSLEEP = 0 15 30 µA
VDVDD Internal logic regulator voltage 2-mA load, VVM > 5.5 V 4.7 5 5.3 V
t(SLEEP) Sleep time nSLEEP low to start device shutdown 50 µs
t(RESET) nSLEEP reset pulse nSLEEP low to only clear fault registers 5 20 µs
t(WAKE) Wake-up time nSLEEP high to device ready for input signals 1.5 ms
ton Turn-on time VM > V(UVLO); nSLEEP = 1, to output transition 1.5 ms
t(DISABLE) DISABLE deglitch time DISABLE signal transition 2.5 µs
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage with respect to VM VVM+5 V
IVCP VCP current VVM = 13.5 V 7 10 mA
f(VCP) Charge pump switching frequency VVM > V(UVLO); nSLEEP = 1 400 kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP, SCLK, SDI)
VIL Input logic-low voltage 0 0.8 V
VIH Input logic-high voltage 1.6 5.3 V
VHYS Input logic hysteresis 150 mV
IIL Input logic-low current VIN = 0 V –5 5 µA
IIH Input logic-high current VIN = 5 V 50 µA
RPD Internal pulldown resistance to GND 100 kΩ
tpd Propagation delay (EN/IN1, PH/IN2 to OUTx = 50%) SR = 000b; IO = 1 A 1.2 µs
SR = 001b; IO = 1 A 1.6
SR = 010b; IO = 1 A 2.6
SR = 011b; IO = 1 A 3.4
SR = 100b; IO = 1 A 4.1
SR = 101b; IO = 1 A 5.2
SR = 110b; IO = 1 A 7.8
SR = 111b; IO = 1 A 13.3
LOGIC-LEVEL INPUT (DISABLE)
RPU,DIS Internal pull-up resistance DISABLE to DVDD 100 kΩ
VIL,DIS Input logic-low voltage 0 0.8 V
VIH,DIS Input logic-high voltage 1.6 5.3 V
LOGIC-LEVEL INPUT (nSCS)
VIL,nSCS Input logic-low voltage 0 0.8 V
VIH,nSCS Input logic-high voltage 1.6 5.3 V
RPU,nSCS Internal pull-up resistance nSCS to nSLEEP 450 kΩ
LOGIC-LEVEL INPUT (nSLEEP)
VIL,SLEEP Input logic-low voltage 0 0.8 V
VIH,SLEEP Input logic-high voltage 2.7 5.3 V
IIH,SLEEP Input logic-high current VIN = 5 V; nSCS is High 80+ISDO(1) µA
THREE-LEVEL INPUT (MODE)
RIN-1 Input mode 1 Tied to GND 105 Ω
RIN-2 Input mode 2 Tied to GND 190 kΩ
RIN-3 Input mode 3 Tied to DVDD 105 Ω
PUSH-PULL OUTPUT (SDO)
RPD,SDO Internal pull-down resistance With respect to GND 30 50 Ω
RPU,SDO Internal pull-up resistance With respect to nSLEEP 120 240 Ω
OPEN DRAIN OUTPUT (nFAULT)
VOL Output logic-low voltage IO = 2 mA 0.1 V
IOZ Output high-impedance leakage VO = 5 V –2 2 µA
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
RDS(ON) High-side FET on-resistance VVM = 13.5 V; TA = 25°C; TJ = 25°C 75 mΩ
VVM = 13.5 V; TA = 25°C; TJ = 150°C 125 155
RDS(ON) Low-side FET on-resistance VVM = 13.5 V; TA = 25°C; TJ = 25°C 75 mΩ
VVM = 13.5 V; TA = 25°C; TJ = 150°C 125 155
t(DEAD) Output dead time SR = 100b 500 ns
VF(DIODE) Body diode forward voltage IO = 1 A 0.8 V
ISINK Sink current when OUTx = Hi-Z nSLEEP = 0 62 µA
nSLEEP = 1, DISABLE = 1 340
SR Slew rate (H/W Device)
OUTx 10% to 90% changing		 IO = 1 A; Connect to GND 53.2 V/µs
IO = 1 A; R(SR) = 22 kΩ ± 5% to GND 34
IO = 1 A; R(SR) = 68 kΩ ± 5% to GND 18.3
IO = 1 A; No connect (Hi-Z) 13
IO = 1 A; R(SR) = 51 kΩ ± 5% to DVDD 7.9
IO = 1 A; Connect to DVDD 2.6
SR Slew rate (SPI Device)
OUTx 10% to 90% changing		 IO = 1 A; SR = 000b 53.2 V/µs
IO = 1 A; SR = 001b 34
IO = 1 A; SR = 010b 18.3
IO = 1 A; SR = 011b 13
IO = 1 A; SR = 100b 10.8
IO = 1 A; SR = 101b 7.9
IO = 1 A; SR = 110b 5.3
IO = 1 A; SR = 111b 2.6
CURRENT SENSE OUTPUTS (IPROPI1, IPROPI2)
k Current mirror scaling 1100 A/A
kERR Current mirror scaling IO < 1 A –50 50 mA
IO ≥ 1 A –5 5 %
t(IPROPI) OUTx to IPROPI VO = 2 V; SR = 000b 2.2 µs
VO = 2 V; SR = 111b 10.5
CURRENT REGULATION
ITRIP Current limit threshold ITRIP_LVL = 00b; VVM = 13.5 V 3.27 3.85 4.43 A
ITRIP_LVL = 01b; VVM = 13.5 V 4.6 5.4 6.2
ITRIP_LVL = 10b; VVM = 13.5 V 5.5 6.5 7.5
ITRIP_LVL = 11b; VVM = 13.5 V 5.95 7 8.1
tOFF PWM off-time TOFF = 00b 20 µs
TOFF = 01b 40
TOFF = 10b 60
TOFF = 11b 80
tBLANK PWM blanking time 5 µs
PROTECTION CIRCUITS
V(UVLO) VM undervoltage lockout VM falling; UVLO report 4.35 4.45 V
VM rising; UVLO recovery 4.5 4.7
t(UVLO) VM UVLO falling deglitch time VM falling; UVLO report 10 µs
V(RST) VM UVLO reset VM falling; UVLO report; device reset 4.1 V
VVCP(UV) Charge pump undervoltage VVM = 12 V; TA = 25°C; CPUV report VVM + 2.25 V
I(OCP) Overcurrent protection trip level 10 A
t(OCP) Overcurrent deglitch time 3 5 µs
t(RETRY) Overcurrent retry time (H/W Device) 4 ms
t(RETRY) Overcurrent retry time (SPI Device) OCP_TRETRY = 00b 0.5 ms
OCP_TRETRY = 01b 1
OCP_TRETRY = 10b 2
OCP_TRETRY = 11b 4
VOLA Open load active mode 150 300 450 mV
td(OL) Open load diagnostic delay time OL_DLY = 0b 0.3 ms
OL_DLY = 1b 1.2
IOL Open load current 3 mA
TOTW Thermal warning temperature Die temperature (TJ) 140 150 160 °C
TTSD Thermal shutdown temperature Die Temperature (TJ) 165 175 185 °C
Thys Thermal shutdown hysteresis Die temperature (TJ) 20 °C
(1) SDO output current external to the device