ZHCSHA0C January   2018  – September 2018 DRV10974


  1. 特性
  2. 应用
  3. 说明
    1.     应用原理图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Speed Input and Control
      2. 7.3.2 Motor Direction Change
      3. 7.3.3 Motor-Frequency Feedback (FG)
      4. 7.3.4 Lock Detection
        1. Lock Kt Measure
        2. Lock No Motor
        3. Lock Open Loop Abnormal
        4. Lock BEMF Abnormal
        5. Lock Closed Loop Abnormal
        6. Lock Speed Abnormal
      5. 7.3.5 Soft Current-Limit
      6. 7.3.6 Short-Circuit Current Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Undervoltage Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Spin-Up Settings
        1. Motor Start
        2. Initial Speed Detect
        3. Align
      2. 7.4.2 Open-Loop Acceleration
      3. 7.4.3 Start-Up Current Sensing
      4. 7.4.4 Closed Loop
      5. 7.4.5 Control Advance Angle
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Speed Input and Control

The DRV10974 device has a three-phase 25-kHz PWM (fPWM_OUT) output that has an average value of sinusoidal waveforms from phase to phase as shown in Figure 4. When any phase is measured with reference to ground, the waveform observed is a PWM-encoded sinusoid coupled with third-order harmonics as shown in Figure 5. This encoding scheme simplifies the driver requirements because one phase output is always equal to zero.

DRV10974 voltage_phase_to_phase_slvsdn2.gifFigure 4. Sinusoidal Voltage
DRV10974 pwm_encoded_phase_output_and_the_av.gifFigure 5. PWM Encoded Phase Output and the Average Value

The output amplitude is determined by the supply voltage (VCC) and the PWM-commanded duty cycle (PWM) as calculated in Equation 1 and shown in Figure 6. The maximum amplitude is applied when the commanded PWM duty cycle is slightly less than 100% in order to keep the 25-kHz PWM rate (fPWM_OUT).

Equation 1. DRV10974 eq_01_vph_slvsdn2.gif
DRV10974 phase_voltage_01.gifFigure 6. Output Voltage Amplitude Adjustment

The motor speed is controlled indirectly by using the PWM command to control the amplitude of the phase voltages which are applied to the motor. The PWM pin can be driven by either a digital duty cycle or an analog voltage.

The duty cycle of the PWM input (PWM) is passed through a low-pass filter that ramps from 0% to 100% duty cycle in 120 ms. The control resolution is approximately 0.2% (DCSTEP). The signal path from PWM input to PWM motor is shown in Figure 7.

DRV10974 fbd_duty_cycle_slvsdn2.gifFigure 7. PWM Command Input Control Diagram

The output peak amplitude is described by Equation 1 when PWMdc > 15% (the minimum-operation duty cycle). When the PWM-commanded duty cycle is lower than the minimum-operation duty cycle and higher than 1.5% (DCON_MIN), the output is controlled the by the minimum-operation duty cycle (DCMIN). This is shown in Figure 8 for analog input, and for duty cycles greater than 1.5% (DCON_MIN) for digital input. If the supply voltage (VVCC) > 14 V, the maximum PWMdc is limited to 14 V / VVCC.

DRV10974 g_duty_cycle_slvsdn2.gifFigure 8. PWM-Mode Speed-Control Transfer Function

When the PWM pin is driven with an analog voltage, the output peak amplitude depends on the supply voltage, the analog voltage on the PWM pin (VANA), and the voltage of V1P8 (VV1P8). This is shown in Equation 2:

Equation 2. DRV10974 eq_02_vph_ana_slvsdn2.gif

Note the output peak amplitude is described by Equation 2 when the VANA > 0.27 V or 15% of 1.8 V. This is the equivalent of the minimum-operation duty cycle percentage of 15% (DCMIN). When the analog voltage on the PWM pin is lower than the minimum-operation duty-cycle percentage but higher than the zero-speed analog voltage (VANA_ZS), the output is controlled by the minimum-operation duty cycle. When the analog voltage on the PWM pin is below zero-speed analog voltage, the DRV10974 enters low-power mode. This is shown in Figure 9.

DRV10974 analog-mode-speed-control-transfer-function-slvsdn2.gifFigure 9. Analog-Mode Speed-Control Transfer Function