SPRSP54 April 2020 DRA80M
ADVANCE INFORMATION for pre-production products; subject to change without notice.
请参考 PDF 数据表获取器件具体的封装图。
The PRU_ICSSG are contains a second layer of multiplexing to enable additional functionality (including MII functionality) on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in Peripherals chapter in the device TRM.
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value).