SPRSP54 April 2020 DRA80M
ADVANCE INFORMATION for pre-production products; subject to change without notice.
请参考 PDF 数据表获取器件具体的封装图。
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC, and not directly through the system interconnect.
For more information, see DDR Subsystem (DDRSS) section in the device TRM.